The CPU can read from non-volatile memory (RRAM) an unlimited number of times, but is restricted in how it writes to memory and the number of writes it can perform.
Writing to RRAM is managed by the RRAM controller (RRAMC), see RRAMC — Resistive random access memory controller.
The Arm® Cortex®-M33 CPU can access RRAM using the C-AHB (code) bus as shown in Memory layout. The code bus (C-AHB) interface is used for any instruction fetch or data access fetch to the code region of the Arm memory model. C-AHB bus access is cached, see CACHE — Instruction/data cache.
RRAM can also be accessed by FLPR. FLPR does not share the instruction cache with the Cortex-M33; it has its own built-in, dedicated cache that is only available to VPR. The regular CACHE — Instruction/data cache is dedicated to the Cortex-M33 and is not available to FLPR.