INTENCLR

nRF54L15 | nRF54L10 | nRF54L05 Datasheet

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW
W1C

STARTED

Write '1' to disable interrupt for event STARTED

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

B

RW
W1C

END

Write '1' to disable interrupt for event END

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

C

RW
W1C

DONE

Write '1' to disable interrupt for event DONE

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

D

RW
W1C

RESULTDONE

Write '1' to disable interrupt for event RESULTDONE

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

E

RW
W1C

CALIBRATEDONE

Write '1' to disable interrupt for event CALIBRATEDONE

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

F

RW
W1C

STOPPED

Write '1' to disable interrupt for event STOPPED

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

G

RW
W1C

CH0LIMITH

Write '1' to disable interrupt for event CH0LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

H

RW
W1C

CH0LIMITL

Write '1' to disable interrupt for event CH0LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

I

RW
W1C

CH1LIMITH

Write '1' to disable interrupt for event CH1LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

J

RW
W1C

CH1LIMITL

Write '1' to disable interrupt for event CH1LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

K

RW
W1C

CH2LIMITH

Write '1' to disable interrupt for event CH2LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

L

RW
W1C

CH2LIMITL

Write '1' to disable interrupt for event CH2LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

M

RW
W1C

CH3LIMITH

Write '1' to disable interrupt for event CH3LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

N

RW
W1C

CH3LIMITL

Write '1' to disable interrupt for event CH3LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

O

RW
W1C

CH4LIMITH

Write '1' to disable interrupt for event CH4LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

P

RW
W1C

CH4LIMITL

Write '1' to disable interrupt for event CH4LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

Q

RW
W1C

CH5LIMITH

Write '1' to disable interrupt for event CH5LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

R

RW
W1C

CH5LIMITL

Write '1' to disable interrupt for event CH5LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

S

RW
W1C

CH6LIMITH

Write '1' to disable interrupt for event CH6LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

T

RW
W1C

CH6LIMITL

Write '1' to disable interrupt for event CH6LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

U

RW
W1C

CH7LIMITH

Write '1' to disable interrupt for event CH7LIMITH

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

V

RW
W1C

CH7LIMITL

Write '1' to disable interrupt for event CH7LIMITL

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled