Pin sensitivity can be individually configured through the SENSE field in the PIN_CNF[n] register to detect a high level or a low level on their input. When the correct level is detected, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal.
The default behavior for the DETECT signal is defined by the register DETECTMODE. By default, the DETECT signals from all pins in the GPIO port are combined into one common DETECT signal that is routed throughout the system, and can be utilized by other peripherals. This mechanism is functional in both System ON and System OFF modes.The DETECTMODE applies to both secure and non-secure pins.
Pins must be in a level that cannot trigger the sense mechanism before enabling it. When the sense mechanism is enabled, the DETECT signal will immediately go high if the SENSE condition configured in the PIN_CNF registers is met. This will trigger a PORT event if the DETECT signal was low before enabling the sense mechanism.
The DETECT signal is used by the power and clock management system to exit from System OFF mode, and by the GPIOTE peripheral to allow pins to generate events and interrupts.
When a pin's PINx.DETECT signal goes high, a flag will be set in the register LATCH. For example, when the PIN0.DETECT signal goes high, bit 0 in the register LATCH will be set to 1. If the CPU performs a clear operation on a bit in the register LATCH when the associated PINx.DETECT signal is high, the bit in the register LATCH will not be cleared. The register LATCH will only be cleared if the CPU explicitly clears it by writing a 1 to the bit to be cleared. This means the register LATCH will not be affected by a PINx.DETECT signal being set low.
The LATCH register has split security. Non-secure code can only read the state of the non-secure pins, while the secure pins read as 0. Secure code is able to read the state of all pins.
The LDETECT signal will be set high when one or more bits in the register LATCH 1. The LDETECT signal will be set low when all bits in the register LATCH are successfully cleared to 0.
If one or more bits in the register LATCH are 1 after the CPU has performed a clear operation, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior.
LDETECT is enabled using the DETECTMODE register. See GPIO port and the GPIO pin details.
The following figure illustrates the DETECT signal behavior for these two alternatives.