TRCCONFIGR

Address offset: 0x010

Controls the tracing options

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																		M	L	K	J	J	I	H	G	G	G	F	E		D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOADASP0INST										Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions.
			No	0								Do not trace load instructions as P0 instructions.
			Yes	1								Trace load instructions as P0 instructions.
B	RW	STOREASP0INST										Instruction P0 field. This field controls whether store instructions are traced as P0 instructions.
			No	0								Do not trace store instructions as P0 instructions.
			Yes	1								Trace store instructions as P0 instructions.
C	RW	BB										Branch broadcast mode bit.
			Disabled	0								Branch broadcast mode is disabled.
			Enabled	1								Branch broadcast mode is enabled.
D	RW	CCI										Cycle counting instruction trace bit.
			Disabled	0								Cycle counting in the instruction trace is disabled.
			Enabled	1								Cycle counting in the instruction trace is enabled.
E	RW	CID										Context ID tracing bit.
			Disabled	0								Context ID tracing is disabled.
			Enabled	1								Context ID tracing is enabled.
F	RW	VMID										Virtual context identifier tracing bit.
			Disabled	0								Virtual context identifier tracing is disabled.
			Enabled	1								Virtual context identifier tracing is enabled.
G	RW	COND										Conditional instruction tracing bit.
			Disabled	0								Conditional instruction tracing is disabled.
			LoadOnly	1								Conditional load instructions are traced.
			StoreOnly	2								Conditional store instructions are traced.
			LoadAndStore	3								Conditional load and store instructions are traced.
			All	7								All conditional instructions are traced.
H	RW	TS										Global timestamp tracing bit.
			Disabled	0								Global timestamp tracing is disabled.
			Enabled	1								Global timestamp tracing is enabled.
I	RW	RS										Return stack enable bit.
			Disabled	0								Return stack is disabled.
			Enabled	1								Return stack is enabled.
J	RW	QE										Q element enable field.
			Disabled	0								Q elements are disabled.
			OnlyWithoutInstCounts	1								Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.
			Enabled	3								Q elements with and without instruction counts are enabled.
K	RW	VMIDOPT										Control bit to select the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators.
			VTTBR_EL2	0								VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always zero. If the trace unit supports a Virtual context identifier larger than 8 bits and if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits [15:8] of the trace unit Virtual context identifier are always zero.
			CONTEXTIDR_EL2	1								CONTEXTIDR_EL2 is used.
L	RW	DA										Data address tracing bit.
			Disabled	0								Data address tracing is disabled.
			Enabled	1								Data address tracing is enabled.
M	RW	DV										Data value tracing bit.
			Disabled	0								Data value tracing is disabled.
			Enabled	1								Data value tracing is enabled.