Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
GRTC : S GRTC : NS	GLOBAL	0x500E2000 0x400E2000	US	S	NA	Yes	Global RTC GRTC

Configuration


Instance	Domain	Configuration
GRTC : S GRTC : NS	GLOBAL	Local CPUs connected to MODE.AUTO.EN.CpuActive : Application core Arm Cortex-M33. CLKSEL settings XO and LFLPRC must be used for lowest possible power consumption in sleep modes. Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 0..14 Number of compare/capture registers : 0..11 Width of the TIMEOUT register : 0..15 Number of GRTC interrupts : 0..3 The PWM registers are available. The CLKOUT register is available. The CLKCFG.CLKSEL register is available. The CLKCFG.CLKSEL register supports LFLPRC. The CC[n].CCADD register has write access only. The ready status and events are available. SYSCOUNTER[n].SYSCOUNTERH.LOADED status is not available CC[n].CCEN.PASTCC status is not available 4 interrupts with interrupt remapping 12 capture compare channels implemented

Register overview


Register	Offset	Description
TASKS_CAPTURE[n]	0x000	Capture the counter value to CC[n] register
TASKS_START	0x060	Start the counter
TASKS_STOP	0x064	Stop the counter
TASKS_CLEAR	0x068	Clear the counter
TASKS_PWMSTART	0x06C	Start the PWM
TASKS_PWMSTOP	0x070	Stop the PWM
SUBSCRIBE_CAPTURE[n]	0x080	Subscribe configuration for task CAPTURE[n]
EVENTS_COMPARE[n]	0x100	Compare event on CC[n] match
EVENTS_RTCOMPARESYNC	0x164	The GRTC low frequency timer is synchronized with the SYSCOUNTER
EVENTS_PWMPERIODEND	0x16C	Event on end of each PWM period
EVENTS_PWMREADY	0x174	Event on STATUS.PWM.READY status changed to ready
EVENTS_CLKOUTREADY	0x178	Event on STATUS.CLKOUT.READY status changed to ready
PUBLISH_COMPARE[n]	0x180	Publish configuration for event COMPARE[n]
PUBLISH_PWMREADY	0x1F4	Publish configuration for event PWMREADY
PUBLISH_CLKOUTREADY	0x1F8	Publish configuration for event CLKOUTREADY
SHORTS	0x200	Shortcuts between local events and tasks
INTEN0	0x300	Enable or disable interrupt
INTENSET0	0x304	Enable interrupt
INTENCLR0	0x308	Disable interrupt
INTPEND0	0x30C	Pending interrupts
INTEN1	0x310	Enable or disable interrupt
INTENSET1	0x314	Enable interrupt
INTENCLR1	0x318	Disable interrupt
INTPEND1	0x31C	Pending interrupts
INTEN2	0x320	Enable or disable interrupt
INTENSET2	0x324	Enable interrupt
INTENCLR2	0x328	Disable interrupt
INTPEND2	0x32C	Pending interrupts
INTEN3	0x330	Enable or disable interrupt
INTENSET3	0x334	Enable interrupt
INTENCLR3	0x338	Disable interrupt
INTPEND3	0x33C	Pending interrupts
EVTEN	0x400	Enable or disable event routing
EVTENSET	0x404	Enable event routing
EVTENCLR	0x408	Disable event routing
MODE	0x510	Counter mode selection
CC[n].CCL	0x520	The lower 32-bits of Capture/Compare register CC[n]
CC[n].CCH	0x524	The higher 32-bits of Capture/Compare register CC[n]
CC[n].CCADD	0x528	Count to add to CC[n] when this register is written.
CC[n].CCEN	0x52C	Configure Capture/Compare register CC[n]
TIMEOUT	0x6A4	Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER
INTERVAL	0x6A8	Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers.
WAKETIME	0x6AC	GRTC wake up time.
STATUS.LFTIMER	0x6B0	Low frequency timer status.
STATUS.PWM	0x6B4	PWM status.
STATUS.CLKOUT	0x6B8	CLKOUT configuration status.
PWMCONFIG	0x710	PWM configuration.
CLKOUT	0x714	Configuration of clock output
CLKCFG	0x718	Clock Configuration
SYSCOUNTER[n].SYSCOUNTERL	0x720	The lower 32-bits of the SYSCOUNTER for index [n]
SYSCOUNTER[n].SYSCOUNTERH	0x724	The higher 20-bits of the SYSCOUNTER for index [n]
SYSCOUNTER[n].ACTIVE	0x728	Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n]