The cache is two-way set associative with a least recently used (LRU) replacement policy. Both instruction and data accesses towards NVM memory are cached.
The cache has the following features:
- 4x64-bit cache line
- Ability to enable/disable cache at run-time
- Writes to cached memory are write-around and invalidate the cache line
- Manual invalidation and erase support
- Locking cache updates on cache misses
- Performance hit/miss counter registers for profiling CACHE operations
- Optional readable cache content for profiling
- Data, tag, valid, and most recently used (MRU) bits
- Can be disabled when not in use
The cache must be enabled by the ENABLE register.