Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
| CPUC | APPLICATION | 0xE0080000 | HF | S | NA | No |
Cortex-M33 configuration |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| EVENTS_FPUIOC | 0x100 |
An invalid operation exception has occurred in the FPU. |
|
| EVENTS_FPUDZC | 0x104 |
A floating-point divide-by-zero exception has occurred in the FPU. |
|
| EVENTS_FPUOFC | 0x108 |
A floating-point overflow exception has occurred in the FPU. |
|
| EVENTS_FPUUFC | 0x10C |
A floating-point underflow exception has occurred in the FPU. |
|
| EVENTS_FPUIXC | 0x110 |
A floating-point inexact exception has occurred in the FPU. |
|
| EVENTS_FPUIDC | 0x114 |
A floating-point input denormal exception has occurred in the FPU. |
|
| INTEN | 0x300 |
Enable or disable interrupt |
|
| INTENSET | 0x304 |
Enable interrupt |
|
| INTENCLR | 0x308 |
Disable interrupt |
|
| LOCK | 0x500 |
Register to lock the certain parts of the CPU from being modified. |
|
| CPUID | 0x504 |
The identifier for the CPU in this subsystem. |