Pin configuration

nRF54L15 | nRF54L10 | nRF54L05 Datasheet

NFCT uses two pins to connect the antenna and these pins are shared with GPIOs.

The ENABLE field in register PADCONFIG defines the usage of these pins and their protection level against excessive voltages. See Pin assignments for the pins used by the NFCT peripheral.

When PADCONFIG.ENABLE=Enabled, a protection circuit will be enabled on the dedicated pins, preventing the chip from being damaged in the presence of a strong NFC field. The protection circuit will short the two pins together if the voltage difference exceeds approximately 2V. The GPIO function on those pins will also be disabled.

When PADCONFIG.ENABLE=Disabled, the device will not be protected against strong NFC field damages caught by a connected NFCT antenna, and the NFCT peripheral will not operate as expected, as it will never leave the DISABLE state.

The pins dedicated to the NFCT antenna function will have some limitation when the pins are configured for normal GPIO operation. The pin capacitance will be higher on those pins (refer to CPAD_NFC in the Electrical Specification of GPIO — General purpose input/output), and some increased leakage current between the two pins is to be expected if they are used in GPIO mode, and are driven to different logical values. To save power, the two pins should always be set to the same logical value whenever entering one of the device power saving modes. For details, refer to INFC_LEAK in the Electrical Specification of GPIO — General purpose input/output.