Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
TWIM20 : S TWIM20 : NS	GLOBAL	0x500C6000 0x400C6000	US	S	SA	No	Two-wire interface controller TWIM20
TWIM21 : S TWIM21 : NS	GLOBAL	0x500C7000 0x400C7000	US	S	SA	No	Two-wire interface controller TWIM21
TWIM22 : S TWIM22 : NS	GLOBAL	0x500C8000 0x400C8000	US	S	SA	No	Two-wire interface controller TWIM22
TWIM30 : S TWIM30 : NS	GLOBAL	0x50104000 0x40104000	US	S	SA	No	Two-wire interface controller TWIM30

Configuration


Instance	Domain	Configuration
TWIM20 : S TWIM20 : NS	GLOBAL	Use GPIO port P1
TWIM21 : S TWIM21 : NS	GLOBAL	Use GPIO port P1
TWIM22 : S TWIM22 : NS	GLOBAL	Use GPIO port P1
TWIM30 : S TWIM30 : NS	GLOBAL	Use GPIO port P0

Register overview


Register	Offset	Description
TASKS_STOP	0x004	Stop TWI transaction. Must be issued while the TWI master is not suspended.
TASKS_SUSPEND	0x00C	Suspend TWI transaction
TASKS_RESUME	0x010	Resume TWI transaction
TASKS_DMA.RX.START	0x028	Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.
TASKS_DMA.RX.STOP	0x02C	Stops operation using easyDMA. This does not trigger an END event.
TASKS_DMA.RX.ENABLEMATCH[n]	0x030	Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.
TASKS_DMA.RX.DISABLEMATCH[n]	0x040	Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.
TASKS_DMA.TX.START	0x050	Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.
TASKS_DMA.TX.STOP	0x054	Stops operation using easyDMA. This does not trigger an END event.
SUBSCRIBE_STOP	0x084	Subscribe configuration for task STOP
SUBSCRIBE_SUSPEND	0x08C	Subscribe configuration for task SUSPEND
SUBSCRIBE_RESUME	0x090	Subscribe configuration for task RESUME
SUBSCRIBE_DMA.RX.START	0x0A8	Subscribe configuration for task START
SUBSCRIBE_DMA.RX.STOP	0x0AC	Subscribe configuration for task STOP
SUBSCRIBE_DMA.RX.ENABLEMATCH[n]	0x0B0	Subscribe configuration for task ENABLEMATCH[n]
SUBSCRIBE_DMA.RX.DISABLEMATCH[n]	0x0C0	Subscribe configuration for task DISABLEMATCH[n]
SUBSCRIBE_DMA.TX.START	0x0D0	Subscribe configuration for task START
SUBSCRIBE_DMA.TX.STOP	0x0D4	Subscribe configuration for task STOP
EVENTS_STOPPED	0x104	TWI stopped
EVENTS_ERROR	0x114	TWI error
EVENTS_SUSPENDED	0x128	SUSPEND task has been issued, TWI traffic is now suspended.
EVENTS_LASTRX	0x134	Byte boundary, starting to receive the last byte
EVENTS_LASTTX	0x138	Byte boundary, starting to transmit the last byte
EVENTS_DMA.RX.END	0x14C	Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed.
EVENTS_DMA.RX.READY	0x150	Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.
EVENTS_DMA.RX.BUSERROR	0x154	An error occured during the bus transfer.
EVENTS_DMA.RX.MATCH[n]	0x158	Pattern match is detected on the DMA data bus.
EVENTS_DMA.TX.END	0x168	Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed.
EVENTS_DMA.TX.READY	0x16C	Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.
EVENTS_DMA.TX.BUSERROR	0x170	An error occured during the bus transfer.
PUBLISH_STOPPED	0x184	Publish configuration for event STOPPED
PUBLISH_ERROR	0x194	Publish configuration for event ERROR
PUBLISH_SUSPENDED	0x1A8	Publish configuration for event SUSPENDED
PUBLISH_LASTRX	0x1B4	Publish configuration for event LASTRX
PUBLISH_LASTTX	0x1B8	Publish configuration for event LASTTX
PUBLISH_DMA.RX.END	0x1CC	Publish configuration for event END
PUBLISH_DMA.RX.READY	0x1D0	Publish configuration for event READY
PUBLISH_DMA.RX.BUSERROR	0x1D4	Publish configuration for event BUSERROR
PUBLISH_DMA.RX.MATCH[n]	0x1D8	Publish configuration for event MATCH[n]
PUBLISH_DMA.TX.END	0x1E8	Publish configuration for event END
PUBLISH_DMA.TX.READY	0x1EC	Publish configuration for event READY
PUBLISH_DMA.TX.BUSERROR	0x1F0	Publish configuration for event BUSERROR
SHORTS	0x200	Shortcuts between local events and tasks
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
ERRORSRC	0x4C4	Error source
ENABLE	0x500	Enable TWIM
FREQUENCY	0x524	TWI frequency. Accuracy depends on the HFCLK source selected.
ADDRESS	0x588	Address used in the TWI transfer
PSEL.SCL	0x600	Pin select for SCL signal
PSEL.SDA	0x604	Pin select for SDA signal
DMA.RX.PTR	0x704	RAM buffer start address
DMA.RX.MAXCNT	0x708	Maximum number of bytes in channel buffer
DMA.RX.AMOUNT	0x70C	Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.
DMA.RX.TERMINATEONBUSERROR	0x71C	Terminate the transaction if a BUSERROR event is detected.
DMA.RX.BUSERRORADDRESS	0x720	Address of transaction that generated the last BUSERROR event.
DMA.RX.MATCH.CONFIG	0x724	Configure individual match events
DMA.RX.MATCH.CANDIDATE[n]	0x728	The data to look for - any match will trigger the MATCH[n] event, if enabled.
DMA.TX.PTR	0x73C	RAM buffer start address
DMA.TX.MAXCNT	0x740	Maximum number of bytes in channel buffer
DMA.TX.AMOUNT	0x744	Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.
DMA.TX.TERMINATEONBUSERROR	0x754	Terminate the transaction if a BUSERROR event is detected.
DMA.TX.BUSERRORADDRESS	0x758	Address of transaction that generated the last BUSERROR event.