The SPU generates a peripheral access error event once access violation is detected.
The following will happen if the logic controlled by the SPU detects an access violation on one
of the peripherals:
- The faulty transfer will be blocked
- In case of a read transfer, the data will read as zero
- If supported by the master, feedback is sent to the master through specific bus error signals. If the master is a processor supporting Arm® TrustZone® for Cortex®-M, a SecureFault exception will be generated for security related errors.
- The PERIPHACCERR event will be triggered.