TRCEVENTCTL1R

nRF54L15 | nRF54L10 | nRF54L05 Datasheet

Address offset: 0x24

Controls the behavior of the events that TRCEVENTCTL0R selects.

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-D

RW

INSTEN[i] (i=0..3)

Instruction event enable field.

Disabled

0

The trace unit does not generate an Event element.

Enabled

1

The trace unit generates an Event element for event i, in the instruction trace stream.

E

RW

DATAEN

Data event enable bit.

Disabled

0

The trace unit does not generate an Event element if event 0 occurs.

Enabled

1

The trace unit generates an Event element in the data trace stream if event 0 occurs.

F

RW

ATB

AMBA Trace Bus (ATB) trigger enable bit.

Disabled

0

ATB trigger is disabled.

Enabled

1

ATB trigger is enabled. If a CoreSight ATB interface is implemented then when event 0 occurs the trace unit generates an ATB event.

G

RW

LPOVERRIDE

Low-power state behavior override bit. Controls how a trace unit behaves in low-power state.

Disabled

0

Trace unit low-power state behavior is not affected. That is, the trace unit is enabled to enter low-power state.

Enabled

1

Trace unit low-power state behavior is overridden. That is, entry to a low-power state does not affect the trace unit resources or trace generation.