Memory and peripheral access permissions

nRF54L15 | nRF54L10 | nRF54L05 Datasheet

Access permissions are controlled by TrustZone, MPC, and SPU security peripherals.

The following figure shows the system security control modules for memory, peripherals, GPIO, and PPI.

Figure 1. Modules filtering access permissions

Modules filtering access permissions

The Arm Cortex®-M33 CPU enforces TrustZone security internally, before issuing bus transactions. For security checks internal to the Arm Cortex-M33, see TrustZone security. After the internal CPU security check, the transaction is available on the bus.

Secure and non-secure memory has to be configured in the SAU and MPC.

The security attribution of a bus transaction from the Arm Cortex-M33 is determined by the CPU, SAU, and IDAU settings. See TrustZone security for more information.

For RISC-V and peripherals, the attribution of the bus transaction is determined by the SPU settings.

The destination's security attribute is a combination of MPC and SPU configurations.

Table 1. Abbreviations
Abbreviation Description
NS Non-secure – TrustZone security attribute is non-secure
S Secure – TrustZone security attribute is secure
NSC Non-secure callable – TrustZone security attribute is non-secure callable
IDAU Arm implementation defined attribution unit
SAU Arm security attribution unit
SPU Nordic system protection unit
MPC Nordic memory privilege controller

Memory access overview

The following table lists the security attributes of the bus manager and their access to memory configured as secure and non-secure.
Table 2. Memory access overview
Bus manager security attribute Destination memory security attribute Access successful MPC bus fault and error event
S S Yes No
NS S No Yes
S NS Yes No
NS NS Yes No

Peripheral access overview

Peripherals are moved in the memory map based on their security association. Non-secure peripherals can be accessed through addresses starting with 0x4 while secure peripherals are accessible in the memory region starting with 0x5.

The security association of each peripheral is controlled via the SPU. Only peripherals with programmable security association can be moved in the memory map.
Table 3. Peripheral access overview
Bus manager security attribute Destination memory security attribute Address region Access successful SPU bus fault and error event
S S 0x5 Yes No
S S 0x4 No Yes
NS S 0x5 No Yes
NS S 0x4 No Yes
S NS 0x5 No Yes
S NS 0x4 Yes No
NS NS 0x5 No Yes
NS NS 0x4 Yes No
In addition, the following also applies:
  • For split security peripherals, bus faults are not generated for blocked split security bit accesses. Reads as 0, write is ignored.
  • In a split peripheral, access is blocked to secure registers using the non-secure 0x4 memory region because it is through non-secure transactions. Make sure to use the secure memory region to access secure registers.