PK.HWCONFIG

Address offset: 0x2018

Hardware configuration register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				N	M	L				K	J	I	H	G	F		E	D	C	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x01F72200				0	0	0	0	0	0	0	1	1	1	1	1	0	1	1	1	0	0	1	0	0	0	1	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MAXOPSIZE										Maximum operand size (number of bytes).
B	R	NBMULT										Number of multipliers:
			MULT1	0								1 multiplier
			MULT4	1								4 multipliers
			MULT16	2								16 multipliers
			MULT64	4								64 multipliers
			MULT256	8								256 multipliers
C	R	PRIMEFIELD										Support prime field.
D	R	BINARYFIELD										Support binary field.
E	R	ECC										Support error correction.
F	R	P256										Support ECC P256 acceleration.
G	R	P384										Support ECC P384 acceleration.
H	R	P521										Support ECC P521 acceleration.
I	R	P192										Support ECC P192 acceleration.
J	R	X25519										Support Curve25519/Ed25519 acceleration.
K	R	AHBMASTER										Memory access
			SLAVE	0								Memory access through AHB Slave and internally in the PKE.
			MASTER	1								Memory access through AHB Master, outside the PKE.
L	R	DISABLESMX										State of DisableSMx input (high when SM2/SM9 operations are disabled).
M	R	DISABLECLRMEM										State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled).
N	R	DISABLECM										State of DisableCM input (high when counter-measures are disabled).