The left right clock (LRCK), often referred to as word clock, sample clock, or word select in I2S context, is the clock defining the frames in serial bitstreams sent and received on SDOUT and SDIN, respectively.
In I2S format, each frame contains one left and/or right sample pair. The left sample is transferred during the low half period of LRCK, followed by the right sample being transferred during the high half period of LRCK.
In Aligned format, each frame contains one left and/or right sample pair. The left sample is transferred during the high half period of LRCK, followed by the right sample being transferred during the low half period of LRCK.
For mono, the frame will contain only zeros for the unused half period of LRCK.
Consequently, the LRCK frequency is equivalent to the audio sample rate.
LRCK = MCK / CONFIG.RATIOLRCK always toggles around the falling edge of the serial clock SCK.