TRCSSCSR0

Address offset: 0x2A0

Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				E																												D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	INST										Instruction address comparator support
			False	0								Single-shot instruction address comparisons not supported.
			True	1								Single-shot instruction address comparisons supported.
B	RW	DA										Data address comparator support
			False	0								Data address comparisons not supported.
			True	1								Data address comparisons supported.
C	RW	DV										Data value comparator support
			False	0								Data value comparisons not supported.
			True	1								Data value comparisons supported.
D	RW	PC										Process counter value comparator support
			False	0								Process counter value comparisons not supported.
			True	1								Process counter value comparisons supported.
E	RW	STATUS										Single-shot status. This indicates whether any of the selected comparators have matched.
			NoMatch	0								Match has not occurred.
			Match	1								Match has occurred at least once.