CPU and support module configuration

The Arm Cortex®-M33 processor has a number of CPU options and support modules implemented on the device.

Table 1. Core options

Option	Description	Implemented
WIC	Wakeup Interrupt Controller	No
Endianness	Memory system endianness	Little endian
DWT	Data Watchpoint and Trace	Yes

Table 2. Modules

Module	Description	Implemented
MPU	Number of non-secure MPU regions	16
	Number of secure MPU regions	16
SAU	Number of SAU regions	4
FPU	Floating-point unit	Yes
DSP	Digital Signal Processing Extension	Yes
Arm TrustZone for Armv8-M	Armv8-M Security Extensions	Yes
CPIF	Coprocessor interface	No
ETM	Embedded Trace Macrocell	Yes
ITM	Instrumentation Trace Macrocell	Yes
MTB	Micro Trace Buffer	No
CTI	Cross Trigger Interface	No
BPU	Breakpoint Unit	Yes
INITSVTOR	Initial secure vector table offset	0x00000000
INITNSVTOR	Initial non-secure vector table offset	0x00000000