Before TWIS can respond to a write command, TWIS must be configured and enabled in the ENABLE register. When enabled, TWIS is in the IDLE state.
A write command is started when TWIM generates a start condition on the TWI bus. This is followed by clocking out the address and setting the READ/WRITE bit to 0 (READ = 1, WRITE = 0). The READ/WRITE bit is followed by an ACK/NACK bit (ACK = 0, NACK = 1) response from the TWIS.
TWIS can listen for two addresses at a time. This is configured in the ADDRESS registers and the CONFIG register.
TWIS only acknowledges (ACK) the write command if the address presented by the controller matches one of the addresses the target is configured to listen for. TWIS will generate a WRITE event when it acknowledges the write command.
TWIS only detects a write command from the IDLE state.
TWIS will set an internal RX prepared flag when the PREPARERX task is triggered.
When the write command is received, TWIS will enter the RX state if the internal RX prepared flag is set.
If the internal RX prepared flag is not set when the write command is received, TWIS will start stretching the master's clock after the first data byte, not allowing the master to send the stop condition. Clock is stretched until the PREPARERX task is triggered and the internal RX prepared flag is set.
TWIS will generate the EVENTS_DMA.RX.READY event and clear the internal RX prepared flag when it enters the RX state. In this state, TWIS will be able to receive the bytes sent by the TWIM.
TWIS returns to the IDLE state if TWIS receives a restart command when it is in the RX state.
TWIS is stopped when it receives the stop condition from TWIM. A STOPPED event will be generated when the transaction has stopped. TWIS will clear the internal RX prepared flag and go back to the IDLE state when it has stopped.
The receive buffer is located in RAM at the address specified in the RXD.PTR register. TWIS can only receive as many bytes as specified in the RXD.MAXCNT register. If TWIM tries to send more bytes to TWIS than it can receive, the extra bytes are discarded and NACKed by the target. If this happens, an ERROR event will be generated.
The EasyDMA configuration registers, RXD.PTR, TXD.PTR, RXD.AMOUNT, and TXD.AMOUNT, are latched when the EVENTS_DMA.RX.READY event is generated.
TWIS can be forced to stop by triggering the STOP task. A STOPPED event will be generated when TWIS has stopped. TWIS will clear the internal RX prepared flag and return to the IDLE state when it has stopped, see Terminate an ongoing TWI transaction.
TWIS will generate an ACK after every byte received from the controller. The RXD.AMOUNT register can be queried after a transaction to see how many bytes were received.
A typical TWIS write command response is illustrated in the following figure, including clock stretching following a SUSPEND task.