The GPIO port peripheral implements up to 32 pins, PIN[n] (n = 0..31),
that can be individually configured in the PIN_CNF[n] registers (n=0..31).
The following parameters can be enabled or configured in these registers:
- Direction
- Drive strength
- Pull-up and pull-down resistors
- Pin sensing
- Input buffer disconnect
- Analog input (for selected pins)
All write-capable registers are retained registers. See POWER — Power control for more information.
When not used as an input, disconnect the input buffer of the GPIO pin to save power. An input must be connected to get a valid value in the IN register and for the sense mechanism to have access to the pin.
Other peripherals in the system can connect to GPIO pins to override their output value, override their configuration, or read their analog or digital input value.
Selected pins also support analog input signals (ANAIN). The assignment of the analog pins can be found in Pin assignments.
GPIO drive strength is configured using the DRIVE0 and DRIVE1 fields of register PIN_CNF[n] (n=0..31) (Retained). Some pins may not support every drive configuration, see Pin assignments for more information.
When a pin is configured as digital input, it is important to minimize increased current consumption when the input voltage is between VIL and VIH. It is a good practice to ensure that the external circuitry does not drive the pin to levels between VIL and VIH for a long period of time.
For more information on pin assignment and the corresponding effect of read and write operations of GPIO registers, see Peripheral and subsystem assignment.