A set of interrupts have been reserved for use as software interrupts.
These interrupts can be enabled and triggered by software by using the Arm® Cortex®-M33 NVIC registers, as described in the Arm Cortex-M33 Processor Technical Reference Manual.
A set of interrupts have been reserved for use as software interrupts.
These interrupts can be enabled and triggered by software by using the Arm® Cortex®-M33 NVIC registers, as described in the Arm Cortex-M33 Processor Technical Reference Manual.