The device implements general detectors to prevent fault injection attacks.
Detectors are strategically placed among the digital logic to detect local timing glitches (timing violations). The glitch detectors monitor the effects of attempted fault injection attacks and not the attack attempt itself. For example, fault injection attempts could be utilizing voltage glitches on supply or decoupling pins, or electro magnetic fault injection (EMFI) techniques. The detectors are designed and tuned to be more sensitive to timing violations than normal logic, enabling the digital logic to react before an injected fault is propagated through the system.
The glitch detectors are enabled from reset and can be disabled for debugging using the registers PROTECT.GLITCHSLOWDOMAIN.CTRL and PROTECT.GLITCHFASTDOMAIN.CTRL.
- A TAMPC EVENT is generated.
- A chip reset is triggered and the SECTAMPER value in the reset reason register indicates what happened, depending on the status of the register PROTECT.INTRESETEN.CTRL.