QFN40 (QDAA) package pin assignments

nRF54L15 | nRF54L10 | nRF54L05 Datasheet

The QFN40 pin assignment figure and table describe the pinouts for this variant of the device.

Pins that can be used as clock signals are shown in as red in the figure. For more information about clock pins, see Clock pins.

Figure 1. QFN40 pin assignments, top view
QFN40 pin assignments, top view
Table 3. QFN40 pin assignments
Pin Clock pin Name Function Description Dedicated function
1

 

P1.00

XL1

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

 

2

 

P1.01

XL2

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

 

3

 

P1.02

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 

4

Yes

P1.03

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 

5

Yes

P1.04

ASO[0]

AIN0

Digital I/O

Digital I/O

Analog input

General purpose I/O

TAMPC active shield 0 output

Analog input

 

TAMPC

 

 

6

 

P1.05

ASI[0]

RADIO[6]

AIN1

Digital I/O

Digital I/O

Digital I/O

Analog input

General purpose I/O

TAMPC active shield 0 input

RADIO DFEGPIO

Analog input

 

TAMPC

RADIO

 

7

 

P1.06

ASO[1]

AIN2

Digital I/O

Digital I/O

Analog input

General purpose I/O

TAMPC active shield 1 output

Analog input

 

TAMPC

 

 

8

Yes

P1.08

 

EXTREF

Digital I/O

Digital I/O

Analog input

General purpose I/O

GRTC CLKOUTFAST

External reference for SAADC

 

9

 

VDD

Power

Power supply

 

10

 

P2.00

 

 

 

 

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

SPIM DCX

UARTE RXD

FLPR.4

QSPI D3

 

SPIM00/20

UARTE00/20

FLPR

FLPR (QSPI)

11

Yes

P2.01

 

 

 

 

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

SPIM SCK

SPIS SCK

FLPR.0

QSPI SCK

 

SPIM00/20

SPIS00/20

FLPR

FLPR (QSPI

12

 

P2.02

 

 

 

 

 

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

SPIM SDO

SPIS SDO

UARTE TXD

FLPR.1

QSPI D0

 

SPIM00/20

SPIS00/20

UARTE00/20

FLPR

FLPR (QSPI)

 

 

13

 

P2.03

 

 

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

FLPR.3

QSPI D2

 

FLPR

FLPR (QSPI)

14

 

P2.04

 

 

 

 

 

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

SPIM SDI

SPIS SDI

UARTE CTS

FLPR.2

QSPI D1

 

SPIM00/20

SPIS00/20

UARTE00/20

FLPR

FLPR (QSPI)

 

15

 

P2.05

 

 

 

 

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

SPIM CSN

SPIS CSN

UARTE RTS

FLPR.5

QSPI CSN

 

SPIM00/20

SPIS00/20

UARTE00/20

FLPR

FLPR (QSPI)

16

Yes

P2.06

 

 

 

TRACECLK

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

FLPR.6

SPIM SCK

SPIS SCK

Trace clock

 

FLPR

SPIM00/21

SPIS00/21

Trace

17

 

P2.07

 

TRACEDATA[0]

SWO

 

 

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

FLPR.7

Trace data

Serial wire output (SWO)

SPIM DCX

UARTE RXD

 

FLPR

Trace

Trace

SPIM00/21

UARTE00/21

18

 

P2.08

 

TRACEDATA[1]

 

 

 

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

Digital I/O

General purpose I/O

FLPR.8

Trace data

SPIM SDO

SPIS SDO

UARTE TXD

 

FLPR

Trace

SPIM00/21

SPIS00/21

UARTE00/21

19

 

VDD

Power

Power supply

 

20

 

P0.00

Digital I/O

General purpose I/O

 

21

 

P0.01

Digital I/O

General purpose I/O

 

22

 

SWDIO

Debug

Serial wire data. Bidirectional with standard-drive and on-chip pull-up.

 

23

 

SWDCLK

Debug

Serial wire clock. Input with on-chip pull-down.

 

24

Yes

P0.04

 

 

Digital I/O

Digital I/O

General purpose I/O

GRTC CLKOUT32K

 

GRTC

25

 

nRESET

Reset

Pin reset with on-chip pull-up

 

26

 

ANT

RF

Single ended radio antenna connection

See Reference circuitry for guidelines on how to ensure good RF performance

27

 

VSS_PA

Power

Ground (radio supply)

 

28

 

DECRF

Power

0.9 V regulator supply decoupling

Must be connected to DECA. See Reference circuitry.

29

 

XC1

Analog input

Connection for 32 MHz crystal

 

30

 

XC2

Analog input

Connection for 32 MHz crystal

 

31

 

VDD

Power

Power supply

 

32

Yes

P1.11

ASO[3]

RADIO[2]

AIN4

Digital I/O

Digital I/O

Digital I/O

Analog input

General purpose I/O

TAMPC active shield 3 output

RADIO DFEGPIO

Analog input

 

TAMPC

RADIO

 

 

33

Yes

P1.12

ASI[3]

RADIO[3]

AIN5

Digital I/O

Digital I/O

Digital I/O

Analog input

General purpose I/O

TAMPC active shield 3 input

RADIO DFEGPIO

Analog input

 

TAMPC

RADIO

 

 

34

 

P1.13

RADIO[4]

AIN6

Digital I/O

Digital I/O

Analog input

General purpose I/O

RADIO DFEGPIO

Analog input

 

RADIO

 

35

 

P1.14

RADIO[5]

AIN7

Digital I/O

Digital I/O

Analog input

General purpose I/O

RADIO DFEGPIO

Analog input

 

RADIO

 

36

 

DECA

Power

0.9 V regulator supply decoupling

Must be connected to DECRF

37

 

VSS

Power

Ground

 

38

 

DECD

Power

0.9 V regulator supply decoupling

 

39

 

DCC

Power

DC/DC regulator output

 

40

 

VDD

Power

Power supply

 

41

 

VSS

Power

Ground pad (die pad)

 

For the device to function properly, the exposed die pad (pin 49) must be connected to ground (VSS, pins 32 and 44).