Memory accesses that violate security permissions will generate a security fault.
If the Arm Cortex-M processor accesses RAM or NVM memory that violate security permissions, and the SAU regions match the device secure/non-secure memory map, the processor generates a SecureFault exception before the transaction enters the system busses.
At the system level, bus accesses are filtered by the Memory Protection Controller (MPC) and System Protection Unit (SPU) security components. These components trigger a BusFault using bus error response, not a SecureFault.
Access to a peripheral register that violates security permissions triggers the SPU event PERIPHACCERR. For more information about the SPU, see SPU — System protection unit. See also Peripherals with split security access.
If a peripheral DMA controller, or the the coprocessor, attempts to access a memory region that is not allowed by the MPC, the MPC will generate a bus error response that triggers a BusFault. The MPC also generates the MEMACCERR event. For more information, see MPC — Memory Privilege Controller.