INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID						R	Q	P	O	N	M	L	K	J	I	H							G			F				E	D	C		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	CTS										Write '1' to disable interrupt for event CTS
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1C	NCTS										Write '1' to disable interrupt for event NCTS
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1C	TXDRDY										Write '1' to disable interrupt for event TXDRDY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW W1C	RXDRDY										Write '1' to disable interrupt for event RXDRDY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW W1C	ERROR										Write '1' to disable interrupt for event ERROR
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW W1C	RXTO										Write '1' to disable interrupt for event RXTO
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW W1C	TXSTOPPED										Write '1' to disable interrupt for event TXSTOPPED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW W1C	DMARXEND										Write '1' to disable interrupt for event DMARXEND
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW W1C	DMARXREADY										Write '1' to disable interrupt for event DMARXREADY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
J	RW W1C	DMARXBUSERROR										Write '1' to disable interrupt for event DMARXBUSERROR When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K-N	RW W1C	DMARXMATCH[i] (i=0..3)										Write '1' to disable interrupt for event DMARXMATCH[i]
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW W1C	DMATXEND										Write '1' to disable interrupt for event DMATXEND
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW W1C	DMATXREADY										Write '1' to disable interrupt for event DMATXREADY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW W1C	DMATXBUSERROR										Write '1' to disable interrupt for event DMATXBUSERROR When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW W1C	FRAMETIMEOUT										Write '1' to disable interrupt for event FRAMETIMEOUT
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled