Multiple power domains ensure low-power operation.
The MCU domain contains an Arm Cortex-M33. The CPU is connected to a debug system that allows debug and ETM trace. The CPU executes program code from RRAM through an instruction cache. Data is stored in single-cycle RAM that is divided into multiple bus subordinates forming a continuous RAM space in the memory map. High-speed peripherals are also found in the MCU domain.
- Radio domain – Contains the short-range radio and supporting peripherals used by the radio protocol stack. It runs at 32 MHz synchronously with the MCU domain.
- Peripheral domain – Contains most peripherals. It runs at 16 MHz synchronously with the MCU domain.
- Low-power domain – Contains peripherals for ultra-low power modes and can be used to wake the rest of the system, even when the peripheral domain is powered off. It runs at 16 MHz asynchronously to the MCU domain.
Each domain is mapped to one APB bus and can be powered independently. EasyDMA traffic from each domain is aggregated in a local AMBIX interconnect and can access RAM in the MCU domain.
Power domains have their own GPIO ports. GPIO pins can be used by peripherals in the same power domain. For exceptions, see GPIO — General purpose input/output and pin assignments.