Architecture

nRF54L15 | nRF54L10 | nRF54L05 Datasheet

The following figure shows the cache architecture.

Figure 1. Cache overview

Cache Overview

Bit Name Description
V Valid Indicates if a cache entry is valid. All V fields are cleared when enabling the cache, invalidating the cache, or when changing CACHE mode.
MRU Most Recently Used Updated on each fetch from the cache to indicate which Way was used most recently. Used to drive the cache replacement policy.