The CCM implements an EasyDMA with scatter/gather mechanism for reading and writing to memory.
In cases where the CPU and other EasyDMA enabled peripherals are accessing the same RAM block at the same time, a high level of bus collisions may cause too slow operation for correct on the fly encryption. In this case the ERROR event will be generated.
EasyDMA will have finished accessing the memory when the END event is generated.
If the IN.PTR and the OUT.PTR are not pointing to memory with DMA connectivity, an EasyDMA transfer may result in a HardFault or memory corruption. See Memory for more information about the different memory regions.
For instances supporting DMA error detection, the ERRORSTATUS register will report if a bus error has occurred during DMA access.