The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode.
The master clock generator always needs to be enabled when in Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when in Slave mode can be useful in the case where the external master is not able to generate its own master clock.
MCK is generated from the CONFIG.MCKFREQ registers.
The following equation can be used to calculate the value of CONFIG.MCKFREQ for given MCK and clock source frequency:
The parameter fMCK is the requested MCK clock frequency in Hz, and fsource is the frequency of the selected clock source in Hz. Because of rounding errors, an accurate MCK clock may not be achievable. The equation does not take into account the maximum register value of CONFIG.MCKFREQ.
The actual MCK frequency can be calculated using the equation below.
The clock error can be calculated using the equation below. The error e is the percentage difference from the requested fMCK frequency.
The master clock generator does not add any jitter to the clock source chosen.
The master clock generator is enabled/disabled using CONFIG.MCKEN, and the generator is started or stopped by the START or STOP tasks respectively.
The MCK frequency can be adjusted on-the-fly by using MCKFREQ.
In Master mode, the LRCK and the SCK frequencies are closely related as both are derived from MCK and set indirectly through CONFIG.RATIO and CONFIG.SWIDTH.
When configuring these registers, the user is responsible for fulfilling the following requirements:
- The SCK frequency can never exceed the MCK frequency.
- The MCK/LRCK ratio shall be a multiple of 2 * CONFIG.SWIDTH.
The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I2S devices that require the MCK to be supplied from the outside.
When operating in Slave mode, the I2S module does not use the MCK and the MCK generator does not need to be enabled.
