Reset behavior

The reset source determines the behavior of the device after a reset.

In System OFF mode, the watchdog timer is not running and CPU lockup is not possible. RAM may be fully or partially retained, depending on RAM retention settings in MEMCONF — Memory configuration.

If the device is in Debug Interface mode, the debug components are not reset. Additionally, CPU lockup does not generate a reset. See Debug and trace for more information about the different debug components in the system.

An 'x' in the table means that the specific module or register is reset. The table also explicitly lists which reset sources are commonly referred to as 'cold boot'.

Table 1. Reset overview

								Retained registers
Reset source	Cold boot	CM33	Peri­pher­als	De­bug	RAM	WDT	REGU­LATORS, OSCI­LLA­TORS and CPU speed	RESET­REAS	POWER.­GP­RET­REG	GPIO	GRTC. SYS­COU­NTER
CPU lockup		x	x							x1	x
Soft reset and CTRL-AP soft reset		x	x							x1
Wakeup from System Off mode		x	x			x
CTRL-AP hard reset		x	x	x	x	x	x			x	x
CTRL-AP pin reset		x	x	x	x	x	x			x	x
Watchdog timer reset		x	x	x	x	x	x			x
Pin reset		x	x	x	x	x	x			x	x
TAMPC reset		x	x	x	x	x	x			x	x
GLITCHDET reset		x	x	x	x	x	x	x	x	x	x
Brownout reset	x	x	x	x	x	x	x	x	x	x	x
Power-on reset	x	x	x	x	x	x	x	x	x	x	x

¹Except the CTRLSEL field.

For TAMPC reset sources, see TAMPC — Tamper controller.