Width, alignment and format

The register CONFIG.SWIDTH defines the sample width of the data read and written to memory, as well as the number of SCK clock cycles per half-frame. Figure Aligned format, with CONFIG.SWIDTH configured to 16 bit samples in a 16 bit half-frame illustrates a configuration with identical sample and half-frame widths. The number of SCK pulses matches the number of sample bits. Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 24-bit half-frame illustrates a configuration with greater half-frame width than sample width. The number of SCK pulses are greater than the number of sample bits, with the sample being left-aligned in the half-frame.

Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 16-bit half-frame. — Figure 7. Aligned format, with CONFIG.SWIDTH configured to 16 bit samples in a 16 bit half-frame

Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 24-bit half-frame. — Figure 8. Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 24-bit half-frame

The register CONFIG.FORMAT is used to choose whether a word shall be aligned on the LRCK edge, or be delayed one bit period after this edge:

When using Aligned format, the first bit in a half-frame gets sampled on the first rising edge of SCK following a LRCK edge, as illustrated in Aligned format. Identical sample width and half-frame width. Left sample on high level of LRCK . The left sample is transferred during the high half period of LRCK.
When using I²S format, the first bit in a half-frame (containing one left or right sample) gets sampled on the second rising edge of the SCK after a LRCK edge, as illustrated in I2S format. Identical sample width and half-frame width. Left sample on low level of LRCK . The left sample is transferred during the low half period of LRCK.

Figure 9. Aligned format. Identical sample width and half-frame width. Left sample on high level of LRCK

I2S format. Identical sample width and half-frame width. — Figure 10. I²S format. Identical sample width and half-frame width. Left sample on low level of LRCK

If the half-frame width differs from the sample width, the sample value can be either right or left-aligned inside a half-frame, as specified in CONFIG.ALIGN

When using left-alignment, each half-frame starts with the MSB of the sample value, as illustrated by CONFIG.ALIGN set to left justified .
When using right-alignment, each half-frame ends with the LSB of the sample value. This is illustrated in CONFIG.ALIGN set to right justified .

CONFIG.ALIGN equaling left justified. — Figure 11. CONFIG.ALIGN set to left justified

CONFIG.ALIGN equaling right justified. — Figure 12. CONFIG.ALIGN set to right justified

Slave mode considerations

In Slave mode, the sample width does not need to equal the half-frame width, or even frame size. This means that there can be extra or fewer SCK pulses per half-frame than what the sample and half-frame widths specified in CONFIG.SWIDTH require.

In cases where left-alignment is used, and the number of SCK pulses per half-frame is higher than the configured width, the following will apply:

For data received on SDIN, all bits after the least significant bit (LSB) of the word value will be discarded.
For data sent on SDOUT, all bits after the LSB of the word value will be 0.

In cases where left-alignment is used, and the number of SCK pulses per frame is lower than the word width, the following will apply:

Data sent and received on SDOUT and SDIN will be truncated with the LSBs being removed first.

In cases where right-alignment is used, and the number of SCK pulses per frame is higher than the configured width, the following will apply:

For data received on SDIN, all bits before the MSB of the word value will be discarded.
For data sent on SDOUT, all bits after the LSB of the word value will be 0 (same behavior as for left-alignment).

In cases where right-alignment is used, and the number of SCK pulses per frame is lower than the configured width, the following will apply:

Data received on SDIN will be sign-extended to the same number of bits as the sample width before being written to memory.
Data sent on SDOUT will be truncated with the LSBs being removed first (same behavior as for left-alignment).