Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
|
P2 : S |
GLOBAL |
0x50050400 |
US | S | NA | Yes |
General purpose input and output, port P2 Does not support pin sense mechanism, and DETECTMODE register has no effect. Supports extra high drive (DRIVE0=E0, DRIVE1=E1). |
|
P1 : S |
GLOBAL |
0x500D8200 |
US | S | NA | Yes |
General purpose input and output, port P1 |
|
P0 : S |
GLOBAL |
0x5010A000 |
US | S | NA | Yes |
General purpose input and output, port P0 |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
|
P2 : S |
GLOBAL |
P2 has 11 pins, P2.00 through P2.10. |
|
P1 : S |
GLOBAL |
I/O pins on this port have pin sense mechanism P1 has 17 pins, P1.00 through P1.16. |
|
P0 : S |
GLOBAL |
I/O pins on this port have pin sense mechanism P0 has 7 pins, P0.00 through P0.06. |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| OUT | 0x000 |
Write GPIO port This register is retained. |
|
| OUTSET | 0x004 |
Set individual bits in GPIO port |
|
| OUTCLR | 0x008 |
Clear individual bits in GPIO port |
|
| IN | 0x00C |
Read GPIO port |
|
| DIR | 0x010 |
Direction of GPIO pins This register is retained. |
|
| DIRSET | 0x014 |
DIR set register |
|
| DIRCLR | 0x018 |
DIR clear register |
|
| LATCH | 0x020 |
Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers This register is retained. |
|
| DETECTMODE | 0x024 | S |
Select between default DETECT signal behavior and LDETECT mode This register is retained. |
| PIN_CNF[n] | 0x080 |
Pin n configuration of GPIO pin This register is retained. |