Address offset: 0x150 + (n × 0x4)
Controls the operation of counter n.
Might ignore writes when the trace unit is enabled or not idle.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | D | C | B | B | B | B | B | B | B | B | A | A | A | A | A | A | A | A | |||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
CNTEVENT |
[0:255] |
Selects an event, that when it occurs causes counter n to decrement. |
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| B |
RW |
RLDEVENT |
[0:255] |
Selects an event, that when it occurs causes a reload event for counter n. |
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| C |
RW |
RLDSELF |
Controls whether a reload event occurs for counter n, when counter n reaches zero. |
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|
Disabled |
0 |
The counter is in Normal mode. |
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|
Enabled |
1 |
The counter is in Self-reload mode. |
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| D |
RW |
CNTCHAIN |
For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs for counter n-1. |
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|
Disabled |
0 |
Counter n does not decrement when a reload event for counter n-1 occurs. |
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|
Enabled |
1 |
Counter n decrements when a reload event for counter n-1 occurs. This concatenates counter n and counter n-1, to provide a larger count value. |
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