STATUS

Address offset: 0x400

The tamper controller status.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.

Note: The glitch detectors must be reset using their CTRL registers before the STATUS register bits for glitch detectors can be cleared. The glitch detector continuously drives its output status signal to the STATUS register, hence clearing only the STATUS register is not sufficient.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				H	G	F	E				D			C	B				A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ACTIVESHIELD										Active shield detector detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.
B	RW W1C	PROTECT										Error detected for the protected signals.
			NotDetected	0								Not detected.
			Detected	1								Detected.
C	RW W1C	CRACENTAMP										CRACEN detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.
D	RW W1C	GLITCHSLOWDOMAIN[i] (i=0..0)										Slow domain glitch detector i detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.
E-H	RW W1C	GLITCHFASTDOMAIN[i] (i=0..3)										Fast domain glitch detector i detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.