Address offset: 0x200C
Status register.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | D | D | D | D | D | C | B | A | A | A | A | A | A | A | A | A | A | A | A | ||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
R |
ERRORFLAGS |
These bits indicate an error condition. They are updated at the end of the operation. They are cleared when starting a new operation. |
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| B |
R |
PKBUSY |
This bit reflects the BUSY output value. It is set when the operation starts and it is cleared when the operation is finished. |
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| C |
R |
INTRPTSTATUS |
This bit reflects the IRQ output value. It is set when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register. |
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| D |
R |
FAILPTR |
These bits indicate which data location generated the error flag. They are not available for all error flags. |
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