Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
|
DPPIC00 : S |
GLOBAL |
0x50042000 |
US | S | NA | Yes |
DPPI controller DPPIC00 |
|
DPPIC10 : S |
GLOBAL |
0x50082000 |
US | S | NA | Yes |
DPPI controller DPPIC10 |
|
DPPIC20 : S |
GLOBAL |
0x500C2000 |
US | S | NA | Yes |
DPPI controller DPPIC20 |
|
DPPIC30 : S |
GLOBAL |
0x50102000 |
US | S | NA | Yes |
DPPI controller DPPIC30 |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
|
DPPIC00 : S |
GLOBAL |
8 DPPI channels 2 DPPI groups |
|
DPPIC10 : S |
GLOBAL |
24 DPPI channels 6 DPPI groups |
|
DPPIC20 : S |
GLOBAL |
16 DPPI channels 6 DPPI groups |
|
DPPIC30 : S |
GLOBAL |
4 DPPI channels 2 DPPI groups |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| TASKS_CHG[n].EN | 0x000 |
Enable channel group n |
|
| TASKS_CHG[n].DIS | 0x004 |
Disable channel group n |
|
| SUBSCRIBE_CHG[n].EN | 0x080 |
Subscribe configuration for task CHG[n].EN |
|
| SUBSCRIBE_CHG[n].DIS | 0x084 |
Subscribe configuration for task CHG[n].DIS |
|
| CHEN | 0x500 |
Channel enable register |
|
| CHENSET | 0x504 |
Channel enable set register |
|
| CHENCLR | 0x508 |
Channel enable clear register |
|
| CHG[n] | 0x800 |
Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled |