Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
|
TWIS20 : S |
GLOBAL |
0x500C6000 |
US | S | SA | No |
Two-wire interface target TWIS20 |
|
TWIS21 : S |
GLOBAL |
0x500C7000 |
US | S | SA | No |
Two-wire interface target TWIS21 |
|
TWIS22 : S |
GLOBAL |
0x500C8000 |
US | S | SA | No |
Two-wire interface target TWIS22 |
|
TWIS30 : S |
GLOBAL |
0x50104000 |
US | S | SA | No |
Two-wire interface target TWIS30 |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
|
TWIS20 : S |
GLOBAL |
Use GPIO port P1 |
|
TWIS21 : S |
GLOBAL |
Use GPIO port P1 |
|
TWIS22 : S |
GLOBAL |
Use GPIO port P1 |
|
TWIS30 : S |
GLOBAL |
Use GPIO port P0 |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| TASKS_STOP | 0x004 |
Stop TWI transaction |
|
| TASKS_SUSPEND | 0x00C |
Suspend TWI transaction |
|
| TASKS_RESUME | 0x010 |
Resume TWI transaction |
|
| TASKS_PREPARERX | 0x020 |
Prepare the TWI slave to respond to a write command |
|
| TASKS_PREPARETX | 0x024 |
Prepare the TWI slave to respond to a read command |
|
| TASKS_DMA.RX.ENABLEMATCH[n] | 0x030 |
Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. |
|
| TASKS_DMA.RX.DISABLEMATCH[n] | 0x040 |
Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. |
|
| SUBSCRIBE_STOP | 0x084 |
Subscribe configuration for task STOP |
|
| SUBSCRIBE_SUSPEND | 0x08C |
Subscribe configuration for task SUSPEND |
|
| SUBSCRIBE_RESUME | 0x090 |
Subscribe configuration for task RESUME |
|
| SUBSCRIBE_PREPARERX | 0x0A0 |
Subscribe configuration for task PREPARERX |
|
| SUBSCRIBE_PREPARETX | 0x0A4 |
Subscribe configuration for task PREPARETX |
|
| SUBSCRIBE_DMA.RX.ENABLEMATCH[n] | 0x0B0 |
Subscribe configuration for task ENABLEMATCH[n] |
|
| SUBSCRIBE_DMA.RX.DISABLEMATCH[n] | 0x0C0 |
Subscribe configuration for task DISABLEMATCH[n] |
|
| EVENTS_STOPPED | 0x104 |
TWI stopped |
|
| EVENTS_ERROR | 0x114 |
TWI error |
|
| EVENTS_WRITE | 0x13C |
Write command received |
|
| EVENTS_READ | 0x140 |
Read command received |
|
| EVENTS_DMA.RX.END | 0x14C |
Generated after all MAXCNT bytes have been transferred |
|
| EVENTS_DMA.RX.READY | 0x150 |
Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
|
| EVENTS_DMA.RX.BUSERROR | 0x154 |
An error occured during the bus transfer. |
|
| EVENTS_DMA.RX.MATCH[n] | 0x158 |
Pattern match is detected on the DMA data bus. |
|
| EVENTS_DMA.TX.END | 0x168 |
Generated after all MAXCNT bytes have been transferred |
|
| EVENTS_DMA.TX.READY | 0x16C |
Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
|
| EVENTS_DMA.TX.BUSERROR | 0x170 |
An error occured during the bus transfer. |
|
| PUBLISH_STOPPED | 0x184 |
Publish configuration for event STOPPED |
|
| PUBLISH_ERROR | 0x194 |
Publish configuration for event ERROR |
|
| PUBLISH_WRITE | 0x1BC |
Publish configuration for event WRITE |
|
| PUBLISH_READ | 0x1C0 |
Publish configuration for event READ |
|
| PUBLISH_DMA.RX.END | 0x1CC |
Publish configuration for event END |
|
| PUBLISH_DMA.RX.READY | 0x1D0 |
Publish configuration for event READY |
|
| PUBLISH_DMA.RX.BUSERROR | 0x1D4 |
Publish configuration for event BUSERROR |
|
| PUBLISH_DMA.RX.MATCH[n] | 0x1D8 |
Publish configuration for event MATCH[n] |
|
| PUBLISH_DMA.TX.END | 0x1E8 |
Publish configuration for event END |
|
| PUBLISH_DMA.TX.READY | 0x1EC |
Publish configuration for event READY |
|
| PUBLISH_DMA.TX.BUSERROR | 0x1F0 |
Publish configuration for event BUSERROR |
|
| SHORTS | 0x200 |
Shortcuts between local events and tasks |
|
| INTEN | 0x300 |
Enable or disable interrupt |
|
| INTENSET | 0x304 |
Enable interrupt |
|
| INTENCLR | 0x308 |
Disable interrupt |
|
| ERRORSRC | 0x4D0 |
Error source |
|
| MATCH | 0x4D4 |
Status register indicating which address had a match |
|
| ENABLE | 0x500 |
Enable TWIS |
|
| ADDRESS[n] | 0x588 |
TWI slave address n |
|
| CONFIG | 0x594 |
Configuration register for the address match mechanism |
|
| ORC | 0x5C0 |
Over-read character. Character sent out in case of an over-read of the transmit buffer. |
|
| PSEL.SCL | 0x600 |
Pin select for SCL signal |
|
| PSEL.SDA | 0x604 |
Pin select for SDA signal |
|
| DMA.RX.PTR | 0x704 |
RAM buffer start address |
|
| DMA.RX.MAXCNT | 0x708 |
Maximum number of bytes in channel buffer |
|
| DMA.RX.AMOUNT | 0x70C |
Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. |
|
| DMA.RX.TERMINATEONBUSERROR | 0x71C |
Terminate the transaction if a BUSERROR event is detected. |
|
| DMA.RX.BUSERRORADDRESS | 0x720 |
Address of transaction that generated the last BUSERROR event. |
|
| DMA.RX.MATCH.CONFIG | 0x724 |
Configure individual match events |
|
| DMA.RX.MATCH.CANDIDATE[n] | 0x728 |
The data to look for - any match will trigger the MATCH[n] event, if enabled. |
|
| DMA.TX.PTR | 0x73C |
RAM buffer start address |
|
| DMA.TX.MAXCNT | 0x740 |
Maximum number of bytes in channel buffer |
|
| DMA.TX.AMOUNT | 0x744 |
Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. |
|
| DMA.TX.TERMINATEONBUSERROR | 0x754 |
Terminate the transaction if a BUSERROR event is detected. |
|
| DMA.TX.BUSERRORADDRESS | 0x758 |
Address of transaction that generated the last BUSERROR event. |