INTENCLR10

Address offset: 0x4B0

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												W	V	U	T	S	R	Q	P	O	N		M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	READY										Write '1' to disable interrupt for event READY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1C	TXREADY										Write '1' to disable interrupt for event TXREADY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1C	RXREADY										Write '1' to disable interrupt for event RXREADY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW W1C	ADDRESS										Write '1' to disable interrupt for event ADDRESS
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW W1C	FRAMESTART										Write '1' to disable interrupt for event FRAMESTART
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW W1C	PAYLOAD										Write '1' to disable interrupt for event PAYLOAD
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW W1C	END										Write '1' to disable interrupt for event END In TX: Last byte to be transmitted has been fetched from RAM In RX: Last byte received on air has been stored to RAM
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW W1C	PHYEND										Write '1' to disable interrupt for event PHYEND
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW W1C	DISABLED										Write '1' to disable interrupt for event DISABLED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
J	RW W1C	DEVMATCH										Write '1' to disable interrupt for event DEVMATCH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K	RW W1C	DEVMISS										Write '1' to disable interrupt for event DEVMISS
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
L	RW W1C	CRCOK										Write '1' to disable interrupt for event CRCOK
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
M	RW W1C	CRCERROR										Write '1' to disable interrupt for event CRCERROR
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
N	RW W1C	BCMATCH										Write '1' to disable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW W1C	EDEND										Write '1' to disable interrupt for event EDEND
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW W1C	EDSTOPPED										Write '1' to disable interrupt for event EDSTOPPED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW W1C	CCAIDLE										Write '1' to disable interrupt for event CCAIDLE
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW W1C	CCABUSY										Write '1' to disable interrupt for event CCABUSY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
S	RW W1C	CCASTOPPED										Write '1' to disable interrupt for event CCASTOPPED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
T	RW W1C	RATEBOOST										Write '1' to disable interrupt for event RATEBOOST
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
U	RW W1C	MHRMATCH										Write '1' to disable interrupt for event MHRMATCH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
V	RW W1C	SYNC										Write '1' to disable interrupt for event SYNC MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered. For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible preamble and the first two bytes of the address field has been received. The event can be generated falsely also in this mode. It is also possible that the event is not generated, or not generated before the ADDRESS event.
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
W	RW W1C	CTEPRESENT										Write '1' to disable interrupt for event CTEPRESENT
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled