The device has dedicated clock pins.
Some peripherals have clock signals. Dedicated clock pins have been optimized to ensure correct timing relationship between clock and data signals for these peripherals. See the following table for which peripheral signals must use clock pins. The pin assignment table identifies clock pins.
Clock pins can also be used as regular I/O data pins.
The peripheral data signal must be configured to use pins close to the clock pin. This ensures that the internal paths from the peripheral to the pin have the same delay, so that the data and clock signals reach the pins at the same time.
For high-speed signals, the printed circuit board (PCB) layout must use short PCB traces of identical length. This makes sure any delays are kept to a minimum, with close to identical delay on the clock and data path.
| Peripheral | Signal | Clock pin required |
|---|---|---|
| SPIM/SPIS | SDO | |
| SDI | ||
| SCK | Yes | |
| CSN | ||
| DCX | ||
| TWIM/TWIS | SCL | Yes |
| SDA | ||
| PDM | DIN | |
| CLK | Yes | |
| I2S | MCK | Yes |
| LRCK | ||
| SCK | Yes | |
| SDIN | ||
| SDOUT | ||
| TRACE | TRACEDATA[] | |
| TRACECLK | Yes (dedicated pin) | |
| GRTC | CLKOUT32K | Yes (dedicated pin) |
| PWMOUT | Yes (dedicated pin) | |
| CLKOUTFAST | Yes (dedicated pin) |