FSYNC defines the start of the frame in the serial bit streams sent and received on
SDOUT and SDIN, respectively. It is often referred to as "word clock", "sample clock", "word
select", "frame clock", or "left/right clock".
In master mode, FSYNC duration is configured in CONFIG.FSYNC.DURATION. The duration can either be one SCK period, or one
channel. This is illustrated in the following figure.
Figure 4. Configuration of FSYNC duration in Master mode
Regardless of FSYNC duration, the frequency of FSYNC is equivalent to the audio sample
rate.
If is possible to configure the sample size to only use a fraction of a channel, see
Width and alignment. Also in this
configuration FSYNC duration is the channel width (not the audio sample size), as
illustrated in the following figure.
Figure 5. FSYNC duration when sample size is less than channel width
The alignment of the frame with the active edge of FSYNC can be adjusted using the
register CONFIG.CHANNEL.DELAY. This allows the data to be delayed one or
more periods of the serial clock following the active edge of FSYNC, as illustrated in
the following figure.
Figure 6. Configuration of delay
When TDM is configured for the I2S mode, each frame contains one left and
right sample pair, with the left sample being transferred during the low half period of
FSYNC followed by the right sample being transferred during the high half period of
FSYNC. There is a single SCK clock pulse delay between FSYNC edge and the first bit of
the sample.
With the Aligned format, each frame contains one left and right sample pair, with the
left sample being transferred during the high half period of FSYNC followed by the right
sample being transferred during the low half period of FSYNC. There is no delay between
FSYNC edge and the first bit of the sample.
For TDM, the active edge of FSYNC defines the beginning of a frame. The words within the
frame are transferred continously, with no transitions of FSYNC.
FSYNC configuration details described above is summarised the following table.