DEBUGIF.DMCONTROL

Address offset: 0x440

Debug Module Control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				K	J	I	H		G	F	F	F	F	F	F	F	F	F	F	E	E	E	E	E	E	E	E	E	E			D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DMACTIVE										Reset signal for the debug module.
			Disabled	0								Reset the debug module itself
			Enabled	1								Normal operation
B	RW	NDMRESET										Reset signal output from the debug module to the system.
			Inactive	0								Reset inactive
			Active	1								Reset active
C	W	CLRRESETHALTREQ										Clear the halt on reset request.
			NoOperation	0								No operation when written 0.
			Clear	1								Clears the halt on reset request
D	W	SETRESETHALTREQ										Set the halt on reset request.
			NoOperation	0								No operation when written 0.
			Set	1								Sets the halt on reset request
E	W	HARTSELHI										The high 10 bits of hartsel.
F	W	HARTSELLO										The low 10 bits of hartsel.
G	W	HASEL										Definition of currently selected harts.
			Single	0								Single hart selected.
			Multiple	1								Multiple harts selected
H	W	ACKHAVERESET										Clear the havereset.
			NoOperation	0								No operation when written 0.
			Clear	1								Clears the havereset for selected harts.
I	RW	HARTRESET										Reset harts.
			Deasserted	0								Reset de-asserted.
			Asserted	1								Reset asserted.
J	W	RESUMEREQ										Resume currently selected harts.
			NoOperation	0								No operation when written 0.
			Resumed	1								Currently selected harts resumed.
K	W	HALTREQ										Halt currently selected harts.
			Clear	0								Clears halt request bit for all currently selected harts.
			Halt	1								Currently selected harts halted.