Instances
| Instance | Domain | Base address | Description |
|---|---|---|---|
| VPRCSR | FLPR |
VPR CSR registers |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
| VPRCSR | FLPR |
VEVIF indexes 16 through 19 maps onto DPPI channels 0 through 4 Use GPIO port P2 HARTNUM: 14 MCLICBASE: 0xF0000000 HIBERNATE: 1 DBG: 1 Number of HW breakpoints: 1 VPR cannot be retained CSR VIOPINS value: 0x000007FF VEVIF tasks: 0..31 Mask of supported VEVIF tasks: 0xFFFFFFFF VEVIF DPPI indices: 16..19 VEVIF events: 0..31 CACHE available OUTMODE for shifting functionality available VPR does not support peripheral blocking access New RTP features CLIC supports 2 level bits |
Register overview
| Register | Offset | Description |
|---|---|---|
| MSTATUS | 0x300 |
Machine Status |
| MISA | 0x301 |
Machine ISA |
| MTVEC | 0x305 |
Machine Trap-Vector |
| MTVT | 0x307 |
Machine Trap Vector Table |
| MCOUNTINHIBIT | 0x320 |
Machine Counter-Inhibit |
| MSCRATCH | 0x340 |
Machine Scratch |
| MEPC | 0x341 |
Machine Exception Program Counter |
| MCAUSE | 0x342 |
Machine Cause |
| MTVAL | 0x343 |
Machine Trap Value |
| MINTSTATUS | 0x346 |
M-mode Interrupt Status |
| MINTTHRESH | 0x347 |
M-mode Interrupt-level Threshold |
| MCLICBASE | 0x350 |
Machine CLIC Base |
| TSELECT | 0x7A0 |
Trigger Select |
| TDATA1 | 0x7A1 |
Trigger Data 1 |
| TDATA2 | 0x7A2 |
Trigger Data 2 |
| TDATA3 | 0x7A3 |
Trigger Data 3 |
| TINFO | 0x7A4 |
Trigger Info |
| TCONTROL | 0x7A5 |
Trigger Control |
| DCSR | 0x7B0 |
Debug Control and Status |
| DPC | 0x7B1 |
Debug PC |
| MCYCLE | 0xB00 |
Machine Cycle Counter |
| MINSTRET | 0xB02 |
Machine Instruction Counter |
| MCYCLEH | 0xB80 |
Machine Cycle Counter (Upper part) |
| MINSTRETH | 0xB82 |
Machine Instruction Counter (Upper part) |
| UCYCLE | 0xC00 |
User Cycle Counter |
| UINSTRET | 0xC02 |
User Instruction Counter |
| UCYCLEH | 0xC80 |
User Cycle Counter (Upper part) |
| UINSTRETH | 0xC82 |
User Instruction Counter (Upper part) |
| MVENDORID | 0xF11 |
Machine Vendor ID |
| MARCHID | 0xF12 |
Machine Architecture ID |
| MIMPID | 0xF13 |
Machine Implementation ID |
| MHARTID | 0xF14 |
Machine Hart ID |
| NORDIC.VPRNORDICCTRL | 0x7C0 |
Nordic Core Control |
| NORDIC.VPRNORDICSLEEPCTRL | 0x7C1 |
Nordic Sleep Control |
| NORDIC.VPRNORDICFEATURESDISABLE | 0x7C2 |
Contains disable bits for certain features in the core |
| NORDIC.VIOPINS | 0x7C3 |
VPR pins used for Real Time Peripherals VIO |
| NORDIC.EXTPARAMS | 0x7C4 |
Reads values of external configuration parameters |
| NORDIC.AXCACHE | 0x7C5 |
Memory type encoding |
| NORDIC.CACHE.CTRL | 0x7C8 |
Cache control |
| NORDIC.CACHE.CFG | 0x7C9 |
Cache configuration |
| NORDIC.CACHE.DATATAGADDR | 0x7CA |
Cache tag base address |
| NORDIC.CACHE.DATABASEADDR | 0x7CB |
Cache data base address |
| NORDIC.RTPERIPHCTRL | 0x7CC |
RT peripheral control |
| NORDIC.RTPERIPHSTATUS | 0x7CD |
Real-Time Peripheral Status |
| NORDIC.CNTMODE0 | 0x7D0 |
CNT0 Mode |
| NORDIC.CNTMODE1 | 0x7D1 |
CNT1 Mode |
| NORDIC.CNT | 0x7D2 |
32-bit Counter |
| NORDIC.CNTTOP | 0x7D3 |
Counter Top |
| NORDIC.CNTADD | 0x7D4 |
CNT Add |
| NORDIC.CNT0 | 0x7D5 |
16-bit Counter 0 |
| NORDIC.CNTADD0 | 0x7D6 |
CNT0 Add |
| NORDIC.CNT1 | 0x7D7 |
16-bit Counter 1 |
| NORDIC.CNTADD1 | 0x7D8 |
CNT1 Add |
| NORDIC.WAIT0 | 0x7DA |
Wait 0 |
| NORDIC.WAIT1 | 0x7DB |
Wait 1 |
| NORDIC.WAIT | 0x7DC |
Wait |
| NORDIC.TASKS | 0x7E0 |
DPPI Tasks |
| NORDIC.SUBSCRIBE | 0x7E1 |
Enable Task Subscription |
| NORDIC.EVENTS | 0x7E2 |
DPPI Events |
| NORDIC.PUBLISH | 0x7E3 |
Enable Event Publication |
| NORDIC.INTEN | 0x7E4 |
DPPI Event Interrupt Enable |
| NORDIC.EVENTSB | 0x7E5 |
Buffered DPPI Events |
| NORDIC.EVENTSBS | 0x7E6 |
EVENTSB Dirty Status |
| NORDIC.OUT | 0xBC0 |
GPIO Output value. Real Time Peripherals VIO. |
| NORDIC.DIR | 0xBC1 |
GPIO pin Direction. Real Time Peripherals VIO. |
| NORDIC.IN | 0xBC2 |
GPIO Input. Real Time Peripherals VIO. |
| NORDIC.INMODE | 0xBC3 |
Input Mode |
| NORDIC.OUTB | 0xBC4 |
Buffered GPIO Output |
| NORDIC.DIRB | 0xBC5 |
Buffered GPIO pin Direction |
| NORDIC.DIROUT | 0xBC6 |
DIR and OUT concatenation |
| NORDIC.DIROUTB | 0xBC7 |
Concatenation of DIRB and OUTB |
| NORDIC.OUTBRB | 0xBC8 |
Byte reversed register OUTB |
| NORDIC.OUTBRW | 0xBC9 |
Word reversed register OUTB |
| NORDIC.INBRB | 0xBCA |
Byte reversed register INB |
| NORDIC.SHIFTCTRLB | 0xBCB |
Buffered IO shift control |
| NORDIC.SHIFTCNTIN | 0xBCD |
Number of frames to be shifted from INB before new data is required |
| NORDIC.SHIFTCNTOUT | 0xBCE |
Number of frames to be shifted to OUTB before new data is required |
| NORDIC.SHIFTCNTB | 0xBCF |
Buffered SHIFTCNTOUT and SHIFTCNTIN register |
| NORDIC.OUTTGL | 0xBD0 |
GPIO Output Toggle |
| NORDIC.DIRTGL | 0xBD1 |
GPIO pin Direction Toggle |
| NORDIC.OUTBTGL | 0xBD2 |
Buffered GPIO Output Toggle |
| NORDIC.DIRBTGL | 0xBD3 |
Buffered GPIO pin Direction Toggle |
| NORDIC.DIROUTTGL | 0xBD4 |
DIROUT Toggle |
| NORDIC.DIROUTBTGL | 0xBD5 |
DIROUTB Toggle |
| NORDIC.OUTUBTGL | 0xBD6 |
Buffered GPIO Unshifted Output Toggle |
| NORDIC.OUTBS | 0xBD8 |
Buffered GPIO Output Dirty Status |
| NORDIC.DIRBS | 0xBD9 |
Buffered GPIO pin Direction Dirty Status |
| NORDIC.DIROUTBS | 0xBDA |
Combination of DIRB and OUTB Dirty Status |
| NORDIC.OUTUBS | 0xBDB |
Buffered GPIO Unshifted Output Dirty Status |
| NORDIC.OUTMODE | 0xBE3 |
Serial output mode |
| NORDIC.OUTMODEB | 0xBE4 |
Buffered OUTMODE register |
| NORDIC.INMODEB | 0xBE5 |
Buffered INMODE register |
| NORDIC.INB | 0xBE6 |
Buffered GPIO input |
| NORDIC.OUTUB | 0xBE7 |
Buffered write to Unshifted parts of OUT |
| NORDIC.SHIFTCNTCOMP | 0xBE8 |
SHIFTCNTIN/OUT compare values |
| NORDIC.WAITEVENT | 0xBE9 |
Wait for internal event |
| NORDIC.WAITINPUT | 0xBEA |
Wait input |
| NORDIC.RTPINTEN | 0xBEB |
Interrupt enable |
| NORDIC.OUTUBTRIG | 0xBEC |
OUTUB trigger select |