SYSCOUNTER

nRF54LM20A | nRF54LM20B Datasheet

The internal counter at SYSCOUNTER increments every 1 µs.

SYSCOUNTER is a 52-bit counter and is enabled using MODE.SYSCOUNTEREN register. The internal low frequency timer must be started for the proper operation of the SYSCOUNTER while SYSCOUNTER goes into sleep mode. It can be started by the TASKS_START task and can be stopped by the TASKS_STOP task when SYSCOUNTER is no more in use.

There are [m] registers SYSCOUNTER[m] providing access to SYSCOUNTER for each security attribute.

The current value of SYSCOUNTER can be read using corresponding SYSCOUNTER[m].SYSCOUNTERL and SYSCOUNTER[m].SYSCOUNTERH. But, the SYSCOUNTER[m].SYSCOUNTERL must be read before corresponding SYSCOUNTER[m].SYSCOUNTERH. The SYSCOUNTER[m].SYSCOUNTERH.OVERFLOW indicates if the SYSCOUNTER[m].SYSCOUNTERL is overflown after reading it.

Sample code for reading the SYSCOUNTER value: 

      uint32_t syscounterl_value, syscounterh_value, syscounterh;
      uint64_t syscounter;

      do
      {
        syscounterl_value = GRTC.SYSCOUNTER[m].SYSCOUNTERL;
        syscounterh = GRTC.SYSCOUNTER[m].SYSCOUNTERH;

        syscounterh_value = ((syscounterh & GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Msk) >> GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Pos);

        if (((syscounterh & GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk) >> GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Pos) == GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Overflow)
        {
          syscounterh = syscounterh_value - 1;
        }

      } while (((syscounterh & GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Msk) >> GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos) != GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Ready);

      syscounter = (syscounterh_value << 32) + syscounterl_value;

Compare and Capture (CC)

The CC[n] is a group of registers interfacing the compare and capture channels of SYSCOUNTER, where n is the number of compare and capture channels specified in the GRTC instance configuration table below. Each CC[n] has an associated TASKS_CAPTURE[n] task and EVENTS_COMPARE[n] event. Each channel compare functionality can be enabled/disabled with CC[n].CCEN.ACTIVE, and its current active state read from this same register.

The EVENTS_COMPARE[n] event can be generated by writing the compare values to the corresponding CC[n].CCL and CC[n].CCH registers. When a channel compare functionality is enabled and SYSCOUNTER is equal or greater than that CC value EVENTS_COMPARE[n] will be generated. Writes to CC[n].CCL disable the corresponding compare channel and writes to CC[n].CCH enable it. So CC[n].CCL must be written first.

Each channel compare functionality, except for the first channel when operating in periodic mode, operates in one-shot mode. When operating in one-shot mode, CC[n].CCEN.ACTIVE is cleared automatically following a compare event.

Moreover, a compare channel is automatically disabled when triggering TASKS_CAPTURE[n].

The EVENTS_COMPARE[n] event is generated immediately if the configured compare value at CC[n] is less than the current SYSCOUNTER value. The status CC[n].CCEN.PASTCC indicates this condition.

Every time the TASKS_CAPTURE[n] task is triggered, the current SYSCOUNTER is copied into the corresponding CC[n].CCL and CC[n].CCH registers. The CC[n].CCL and CC[n].CCH registers can be read in any order. The TASKS_CAPTURE[n] task will not generate EVENTS_COMPARE[n] event.

The TASKS_CAPTURE[n] tasks and EVENTS_COMPARE[n] events can be connected with the PPI. However, the TASKS_CAPTURE[n] is functional only when the SYSCOUNTER is in active state. The GRTC can be forced into active state by setting any SYSCOUNTER[n].ACTIVE register.

The compare value for CC[n] can also be updated by adding a fixed value provided at CC[n].CCADD.VALUE. Based on the CC[n].CCADD.REFERENCE configuration, either the current CC value or the current SYSCOUNTER value is added to the CC[n].CCADD.VALUE to configure the new compare value. Writing to CC[n].CCADD enables the corresponding compare channel.

Writes to CC[n].CCADD are ignored when the SYSCOUNTER is in sleep state.

Periodic interval

In addition to one-shot mode, the CC[0] can produce periodic EVENTS_COMPARE[0] event without any software interaction. The interval between these events can be programmed using INTERVAL register and non-zero interval enables this periodic interval feature. On every EVENTS_COMPARE[0] event, CC[0] becomes CC[0] + INTERVAL.

SYSCOUNTER sleep mode

SYSCOUNTER supports the following power modes:
  • SYSCOUNTER is in active state
  • SYSCOUNTER is in sleep state - This is the GRTC ultra-low power sleep mode

To save power, SYSCOUNTER automatically goes into sleep state when there is no activity.

Before SYSCOUNTER goes into sleep state, the GRTC configures the internal low frequency timer compare match based on the next expected SYSCOUNTER compare match using CC[n] configuration. An internal event on low frequency timer is generated when the compare match happens.

The internal counter at SYSCOUNTER is not ticking when SYSCOUNTER is in sleep state, the internal low frequency timer is configured as described above.

SYSCOUNTER returns to active state when any one of the following condition is met, SYSCOUNTER goes back into sleep state when none of the above conditions met. However, the SYSCOUNTER active state can be extended by configuring the number of LFCLK cycles at TIMEOUT register.

On wake up to active state, SYSCOUNTER is updated based on the internal low frequency timer compare match. The status SYSCOUNTER[m].SYSCOUNTERH.BUSY indicates SYSCOUNTER is synchronized and valid after the SYSCOUNTER is woken up.

The status SYSCOUNTER[m].SYSCOUNTERH.LOADED indicates SYSCOUNTER is loaded after wake up, but not synchomized to the low frequency clock yet. This gives early indication of the SYSCOUNTER value, whcih may vary approximately one low frequency clcok cycle.

The SYSCOUNTER status can be summerized as below:

Before handling next scheduled EVENTS_COMPARE[n] event, GRTC must wake up from the low power state. The WAKETIME register configures the number of LFCLK cycles that GRTC will wake up before the compare event. This duration allows the device sufficient time to power up, initialize, and activate the necessary clocks to accurately generate and handle events from the GRTC SYSCOUNTER. A longer system wake-up time requires a larger WAKETIME value to ensure reliable event processing. When the device is in System OFF, the WAKETIME must cover the system wakeup time from System OFF mode and in addition the required time the system uses to configure GRTC and enable the event.

All GRTC registers must be restored at wakeup from system OFF before the next scheduled COMPARE[n] event is generated. The TIMEOUT register must be configured to a value higher than WAKETIME (TIMEOUT > WAKETIME + guard_time). This makes sure that GRTC is not entering sleep again if the next event is nearer than TIMEOUT LFCLK cycles. The minimum guard time is 1 LFCLK cycle.

Recommendation on reading SYSCOUNTER

The following steps are recommended while reading SYSCOUNTER:
  1. Set the corresponding SYSCOUNTER[m].ACTIVE to Active
  2. Wait until the corresponding status SYSCOUNTER[m].SYSCOUNTERH.BUSY is cleared
  3. Read the corresponding SYSCOUNTER[m].SYSCOUNTERL/H values
  4. Clear the SYSCOUNTER[m].ACTIVE set above

Entering System OFF mode

The following steps are recommended before entering System OFF mode:
  1. Set the SYSCOUNTER in active state, either
  2. If GRTC is wakeup source, then set the corresponding CC[n] value to expected wakeup time
  3. Set WAKETIME for the boot latency
  4. Set the SYSCOUNTER in sleep state, by clearing the configuration set at step 1 above
  5. Wait for either of EVENTS_RTCOMPARESYNC or any EVENTS_COMPARE[n]
    • If any EVENTS_COMPARE[n] triggered,
      1. Allow CPUs to wakeup on interrupts
      2. Do not enter System OFF mode
    • Else,
      1. Enter System OFF by using the SYSTEMOFF register