DIEPCTL0

nRF54LM20A | nRF54LM20B Datasheet

Address offset: 0x900

Device Control IN Endpoint 0 Control Register

This register is used to control the characteristics of the IN Endpoint 0 of the Device controller.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID J I H G F F F F E D D C B A A
Reset 0x00008000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

MPS

Maximum Packet Size (MPS)

Applies to IN and OUT endpoints. The application must program this field with the maximum packet size for the current logical endpoint.

BYTES64

0

64 bytes

BYTES32

1

32 bytes

BYTES16

2

16 bytes

BYTES8

3

8 bytes

B

R

USBACTEP

USB Active Endpoint (USBActEP)

This bit is always SET to 1, indicating that control endpoint 0 is always active in all configurations and interfaces.

ACTIVE0

1

Control endpoint is always active

C

R

NAKSTS

NAK Status (NAKSts)

Indicates the following: When this bit is set, either by the application or core, the core stops transmitting data, even If there is data available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

INACTIVE

0

The core is transmitting non-NAK handshakes based on the FIFO status

ACTIVE

1

The core is transmitting NAK handshakes on this endpoint

D

R

EPTYPE

Endpoint Type (EPType)

Hardcoded to 00 for control.

ACTIVE

0

Endpoint Control 0

E

RW

STALL

STALL Handshake (Stall)

The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.

INACTIVE

0

No Stall

ACTIVE

1

Stall Handshake

F

RW

TXFNUM

TxFIFO Number (TxFNum)

- For Shared FIFO operation, this value is always set to 0, indicating that control IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO. - For Dedicated FIFO operation, this value is set to the FIFO number that is assigned to IN Endpoint.

TXFIFO0

0

Tx FIFO 0

TXFIFO1

1

Tx FIFO 1

TXFIFO2

2

Tx FIFO 2

TXFIFO3

3

Tx FIFO 3

TXFIFO4

4

Tx FIFO 4

TXFIFO5

5

Tx FIFO 5

TXFIFO6

6

Tx FIFO 6

TXFIFO7

7

Tx FIFO 7

TXFIFO8

8

Tx FIFO 8

TXFIFO9

9

Tx FIFO 9

TXFIFO10

10

Tx FIFO 10

TXFIFO11

11

Tx FIFO 11

TXFIFO12

12

Tx FIFO 12

TXFIFO13

13

Tx FIFO 13

TXFIFO14

14

Tx FIFO 14

TXFIFO15

15

Tx FIFO 15

G

W

CNAK

Clear NAK (CNAK) A write to this bit clears the NAK bit for the endpoint.

NOCLEAR

0

No action

CLEAR

1

Clear NAK

H

W

SNAK

Set NAK (SNAK) A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

NOSET

0

No action

SET

1

Set NAK

I

RW

EPDIS

Endpoint Disable (EPDis)

The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled Interrupt. The application must Set this bit only if Endpoint Enable is already set for this endpoint.

INACTIVE

0

No action

ACTIVE

1

Disabled Endpoint

J

RW

EPENA

Endpoint Enable (EPEna)

When Scatter/Gather DMA mode is enabled for IN endpoints, this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. When Scatter/Gather DMA mode is disabled (such as in buffer pointer based DMA mode) this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting the following interrupts on this endpoint: - Endpoint Disabled - Transfer Completed

INACTIVE

0

No action

ACTIVE

1

Enable Endpoint