GSTARFXDIS

RW

HOSTIGNORESRMTWKUPDIS

Disable the STAR fix added for Device controller to go back to low power mode when Host ignores Remote wakeup

The application programs Host_Ignores_RmtWkup_dis=1 to disable the device controller from going back to low power mode (SUSPENDED state) when the host ignores the remote wakeup signalling from the device and does not respond back with resume. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

RESUMEFRMCHKBUSDIS

Disable the STAR fix added for Device controller to detect lineK and move to RESUMING state after the 50us pull-up delay ends

The application programs Resume_frm_CHK_BUS_dis=1 to disable the device controller from detecting line K and transitioning to RESUMING state in the scenario where Host resume starts immediately after the 50us pull-up delay timer expires. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

IGNORECTLOUTDATA0DIS

Disable the STAR fix added for Device controller to reject DATA0 for the first Control OUT Data Phase and Control Status OUT Phase

The application programs Ignore_CtlOUT_DATA0_dis=1 to disable the device controller from reporting transaction error when DATA0 PID is received from host for the first Control OUT Data Phase and Control Status OUT phase. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

SSPLITSTALLNYETERRDIS

Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET

The application programs SSPLIT_STALLNYET_Err_dis=1 to disable the host controller from reporting transaction error for STALL/NYET received from device for SSPLIT transfer. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

ACCEPTISOCSPLITDATA1DIS

Disable the STAR fix added for Host controller to accept DATA1 PID from device for ISOC Split transfers

The application programs Accept_Isoc_split_DATA1_dis=1 to disable the host controller from accepting DATA1 PID from device for ISOC Split transfers. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

HANDLEFAULTYCABLEDIS

Disable the STAR fix added for Host controller to handle Faulty cable scenarios

The application programs HandleFaultyCable_dis=1 to disable the host controller from reporting Port Babble error when the linestate is stuck at 1 (in FS mode) or 2 (in LS mode) due to a Faulty cable. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

LSIPGINCRDIS

Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit times to 3 LS bit times

The application programs LS_IPG_incr_dis=1 to disable the IPG increment from 2 to 3 LS bit times when host controller is operating in LS mode. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

FSDISCIDLEDIS

Disable the STAR fix added for Device controller to transition to IDLE state during FS device disconnect

The application programs FSDisc_Idle_dis=1 to disable the Transmit/Receive state machine from moving to IDLE state when FS device disconnect happens. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

CONCURRENTRMTWKUPUSBRESUMEDIS

Disable the STAR fix added for Device controller to not start Remote Wakeup signalling when USB resume has already started

The application programs Concurrent_Rmtwkup_USBResume_dis=1 to allow the controller to do remote wakeup signalling when USB resume has already started from the Host. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

LSIPGCHKAFTERNAKSTALLFORINDIS

Disable the STAR fix added for Host controller to wait for IPG duration to send next token after receiving NAK/STALL for previous IN token with FS/LS device

The application programs LS_IPG_chk_after_NAK_STALL_for_IN_dis=1 to allow the controller to send the next token without waiting for the interpacket gap duration after receiving a NAK/STALL from device for the previous IN token. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

PHYIOPXCVRSELTXVLDCORRDIS

Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrselect switching and utmi_txvalid assertion in LS/FS mode

The application programs PHY_IOp_xcvrsel_txvld_corr_dis=1 to allow the controller to assert utmi_txvalid 1 cycle after the utmi_xcvrselect switching. This can cause interop issues with SNPS PHY which requires at least 2 cycles of gap between the utmi_xcvrselect switch and the utmi_txvalid assertion. Hence it is recommended to program PHY_IOp_xcvrsel_txvld_corr_dis=0. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

ULPIXCVRSELSWITCHCORRDIS

Disable the STAR fix added for Host controller to increase the preamble transceiver select switch delay to accommodate time taken for ULPI function control write

The application programs ULPI_xcvrsel_switch_corr_dis=1 to allow the controller to do back to back transceiver select switching within the duration required for a single ULPI function control write (around 5-6 ulpi_clk cycles). This can cause a corrupted packet to go on the bus since the ULPI wrapper may not be able to do the second ULPI functional update (register write) correctly. Hence it is recommended to program ULPI_xcvrsel_switch_corr_dis=0. With ULPI_xcvrsel_switch_corr_dis=0, the delay between transceiver select switch and txvalid assertion has also been increased for FS/LS mode to resolve PHY interop issues. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

XACTERRDATA0CTRLSTSINDIS

Disable the STAR fix added for Host controller to report transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode

The application programs XactErr_DATA0_CTRL_STS_IN_dis=1 to allow the controller to respond with ACK for the incorrect DATA0 PID and then retry the control STATUS IN transfer until DATA1 PID is received. With XactErr_DATA0_CTRL_STS_IN_dis=0, the controller generates Transaction Error interrupt when the incorrect PID is received. This STAR fix is applicable only for Buffer DMA and Descriptor DMA modes. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

HOSTUTMITXVLDCORRDIS

Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode.

When HPRT.PrtRst is set by the application, the Host controller can change the Opmode, XcvrSel and TermSel while TxValid is still high (1'b1) during SOF transmission in 8-bit UTMI mode. This behavior of the controller has been corrected to handle port reset during SOF transmission. With the fix, the controller waits for Txvalid to go low (1'b0) and then changes the OpMode, XcvrSel and TermSel. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

OPMODEXCVRSELCHIRPENCORRDIS

Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when reset is detected in suspend state.

In configurations with Battery charger support enabled (and GOTGCTL.ChirpEn programmed to 1), the RTL has been updated to wait for 1ms and then change the opmode and xcvrselect when reset is detected in the suspend state. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller and change Opmode and XcvrSel without waiting for 1ms after reset detection. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

TXVALIDDEASSERTIONCORRDIS

Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when soft disconnect is done.

The RTL has been updated to wait for utmi_txready and then de-assert the utmi_txvalid being driven by MAC DSSR when soft disconnect is done. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller and change Txvalid without waiting for Txready. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

HOSTNOXFERAFTERPRTDISFIXDIS

Disable the STAR fix added for correcting Host behavior when port is disabled.

The RTL has been updated to not assert utmi_txvalid when the port is disabled. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

LINESTATESE0FILTERFOREOPDIS

Disable the STAR fix added for filtering SE0 from the linestate during EOP detection..

The RTL has been updated to filter glitches occurred in the linestate. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

DMPULLDOWNUPDATEINOTGFORHIBANDPP

Disable the STAR fix added for utmiotg_dmpulldown update in Hibernation and Partial power down modes.

The RTL has been updated for OTG mode to remove the glitch in utmiotg_dmpulldown signal while controller is exiting from Hibernation or Partial power down. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

CHIRPDETECTIONUPDTHSTDIS

Disable the Chirp detection logic change in host mode.

The RTL has been updated in Host mode to avoid the unexpected chirp detection when there is no chirp K from device. After the RTL fix chirp detection logic depends on the delayed WAIT_CHIRP state. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

PROGRAMMABLESE0DURATIONTODETECTEOP

Disable the STAR fix added for programmable se0 duration to detect EOP in Host mode .

The RTL Enhancement has been done to reduce the EOP SE0 detection time for USB2 SOF,transmitted by the core to work with longer cables and/or devices with longer delays. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT

Disable the STAR fix added for h2pd_txf_0len_pkt signal which is passing through a level synchronizer.

Dummy synchronizer of h2pd_txf_0len_pkt signal has been replaced with Level synchronizer. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

EUSB2TERMINATERESUMEONDISCDIS

Disable fix for Terminating Resume if UTMI HostDisconnect is detected.

The RTL has been updated in Host mode to terminate Resume if UTMI HostDisconnect is asserted, this is to avoid the controller and PHY from being out of sync if HostDisconnect coincides with the beginning of Resume transmission. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

EUSB2FSLSDISCDETECTIONDIS

Disable fix for FS/LS disconnect detection using UTMI HostDisconnect in MAC PRT.

The RTL has been updated in Host mode to detect disconnect using the utmi_hostdisconnect signal instead of monitoring 2.5us of SE0 on DP/DM. The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

HOSTFLUSHEXCESSTKNFIXDIS

Disable fix for recovering the Host controller when sufficient time is not available in the current uF for an overscheduled ISOC OUT or INTR IN transfer.

The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

TITRANSDONETGLDURINGISOCEOPFDISABLE

Disable the fix added to not toggle ti_trans_done in SEND_EOP state when the ISOC in tokens responds with zero length packets after end of periodic frame till next start of frame. The fix is added when operating in descriptor dma device mode.

The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.

RW

CLEARSOFREFCLKTIMERDURINGDISC

Disable the STAR fix added to clear the SOF refclk timer during disconnect detection. The STAR fix is added when using both UTMI and eUSB2 PHY.

The application can set this register bit to 1'b1 to fall back to the original behavior of the controller. This bit must be programmed during the initial configuration of the controller and must not be modified later.