The PKE data RAM is used by CRACEN as a store for intermediate values when doing cryptographic operations.
The PKE data RAM is divided into 15 different pages of size 4096 bits, where each page
holds different data types for asymmetric cryptographic operations. After CRACEN IKG has been
started, the PKE operate in what is referred to as CRACEN Secure Mode. In CRACEN Secure Mode,
PKE RAM pages 0x8 - 0xC are accessible to the CPU, and will hold both the IAK public key
components and the digest to be signed in addition to the signature components. The following
table lists all pages and their availability from CPU access in CRACEN Secure Mode. To avoid
information leakage, some of the pages are automatically zeroized when CRACEN is exiting
Secure Mode.
| Page number | Access | Zeroization |
|---|---|---|
| 0-7 | Blocked from CPU access | Yes |
| 8-12 | Accessible from the CPU | No |
| 13-15 | Blocked from CPU access | Yes |