INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																									G	F	E		D			C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	RXPTRUPD										Write '1' to enable interrupt for event RXPTRUPD
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	STOPPED										Write '1' to enable interrupt for event STOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1S	ABORTED										Write '1' to enable interrupt for event ABORTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW W1S	TXPTRUPD										Write '1' to enable interrupt for event TXPTRUPD
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW W1S	MAXCNT										Write '1' to enable interrupt for event MAXCNT
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW W1S	BUSERROR_RX										Write '1' to enable interrupt for event BUSERROR_RX When this event is generated, the address which caused the error can be read from the RXD.BUSERRORADDRESS register.
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW W1S	BUSERROR_TX										Write '1' to enable interrupt for event BUSERROR_TX When this event is generated, the address which caused the error can be read from the TXD.BUSERRORADDRESS register.
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled