The general purpose input/output (GPIO) pins are grouped as one or more ports, with each port having up to 32 GPIO pins.
The number of ports and GPIO pins per port varies with product variant and package. Refer to Registers and Pin assignments for more information about the number of GPIO pins that are supported.
GPIO has the following user-configurable features:
- Configurable output drive strength
- Internal pull-up and pull-down resistors
- Wake-up from high or low level triggers on all pins in PERI and LP power domains
- Trigger interrupt on state changes on any pin on selected ports, see the wakeup source capability in Port capabilities
- One or more GPIO outputs can be controlled through PPI and GPIOTE channels
- All pins can be individually mapped to interface blocks for layout flexibility
- GPIO state changes captured on SENSE signal can be stored by LATCH register
- Support for secure and non-secure attributes for pins in conjunction with the system protection unit (SPU)
The following figure illustrates the GPIO port containing 32
individual pins, where PIN0 is illustrated in more detail as a reference. All
signals on the left side in the illustration are used by other peripherals in the system and
therefore not directly available to the CPU.