CONFIG.CHANNEL.DELAY

Address offset: 0x534

Set channel delay.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	DELAY										Configure number of inactive SCK periods from edge of FSYNC until start of first data bit.
			Delay0Ck	0								No delay. Used with I2S DSP/Aligned format.
			Delay1Ck	1								One clock pulse delay. Used with Original I2S format.
			Delay2Ck	2								Two clock pulses delay.