The device implements glitch detectors to protect against fault injection attacks.
Detectors are strategically placed to detect fault injection attacks. The detectors are designed and tuned to trigger before logic fails enabling the digital logic to react before an injected fault is propagated through the system.
The glitch detectors are enabled from reset and can be disabled for debugging using
When an internal tamper event is detected, one of the following will occur:
- A TAMPC EVENT is generated.
- A chip reset is triggered and the SECTAMPER value in the reset reason register indicates what happened, depending on the status of the register PROTECT.INTRESETEN.CTRL.