DOEPCTL13

nRF54LM20A | nRF54LM20B Datasheet

Address offset: 0xCA0

Device Control OUT Endpoint Control Register 13

This register is used to control the characteristics of OUT Endpoint 13 of the Device controller.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID L K J I H G F E E D C B A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

MPS

Maximum Packet Size (MPS)

The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

B

RW

USBACTEP

USB Active Endpoint (USBActEP)

Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit.

DISABLED

0

Not Active

ENABLED

1

USB Active Endpoint

C

R

DPID

Endpoint Data PID (DPID)

Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The applications use the SetD1PID and SetD0PID fields of this register to program either DATA0 or DATA1 PID. This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather DMA mode: - Applies to isochronous IN and OUT endpoints only. - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register. - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

INACTIVE

0

Endpoint Data PID not active

ACTIVE

1

Endpoint Data PID active

D

R

NAKSTS

NAK Status (NAKSts)

Indicates the following: When either the application or the core sets this bit: - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

NONNAK

0

The core is transmitting non-NAK handshakes based on the FIFO status

NAK

1

The core is transmitting NAK handshakes on this endpoint

E

RW

EPTYPE

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

CONTROL

0

Control

ISOCHRONOUS

1

Isochronous

BULK

2

Bulk

INTERRUPT

3

Interrupt

F

RW

STALL

STALL Handshake (Stall)

Applies to non-control, non-isochronous IN and OUT endpoints only. The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only. The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

INACTIVE

0

STALL All non-active tokens

ACTIVE

1

STALL All Active Tokens

G

W

CNAK

Clear NAK (CNAK) A write to this bit clears the NAK bit for the endpoint.

INACTIVE

0

No Clear NAK

ACTIVE

1

Clear NAK

H

W

SNAK

Set NAK (SNAK)

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

INACTIVE

0

No Set NAK

ACTIVE

1

Set NAK

I

W

SETD0PID

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only. - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0. - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) - Applies to isochronous IN and OUT endpoints only. - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame. - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

DISABLED

0

Disables Set DATA0 PID or Do not force Even Frame

ENABLED

1

Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame

J

W

SETD1PID

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only. - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1. - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode. Set Odd (micro)frame (SetOddFr) - Applies to isochronous IN and OUT endpoints only. - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

DISABLED

0

Disables Set DATA1 PID or Do not force Odd Frame

ENABLED

1

Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame

K

RW

EPDIS

Endpoint Disable (EPDis)

Applies to IN and OUT endpoints. The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

INACTIVE

0

No Action

ACTIVE

1

Disable Endpoint

L

RW

EPENA

Endpoint Enable (EPEna)

Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled, - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup. When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode: - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint. - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB. The core clears this bit before setting any of the following interrupts on this endpoint: - SETUP Phase Done - Endpoint Disabled - Transfer Completed Note: For control endpoints in DMA mode, this bit must be set for the controller to transfer SETUP data packets to the memory. This bit is not cleared on Transfer Completed interrupt of the SETUP packet.

INACTIVE

0

No Action

ACTIVE

1

Enable Endpoint