The PDM clock frequency is adjusted through the PRESCALER register in the master clock. The master clock generator does not add jitter to the selected HFCLK source. It is recommended (but not mandatory) to use the crystal as HFCLK source.
The PDM frequency can be adjusted by using the PRESCALER register, even while the clock
generator is running. To select the correct value for PRESCALER, use the following equation:
- CLK=PCLK32M/PRESCALER when using PCLK32M
- CLK=ACLK/PRESCALER when using a second CLK source
Note: Depending on the product, ACLK can be connected to different
clock sources. For example, ACKL can be connected to a PLL generating a 24 MHz
clock.
| Requested PDM frequency fpdm [Hz] | fsource [Hz] | RATIO | PRESCALER | Actual PDM frequency factual [Hz] | Sample frequency [Hz] | Error [%] |
|---|---|---|---|---|---|---|
| 1024000 | 32000000 (PCLK32M) | 64 | 31 | 1032258 | 16129 | 0.8 |
| 1280000 | 32000000 (PCLK32M) | 80 | 25 | 1280000 | 16000 | 0 |
| 800000 | 32000000 (PCLK32M) | 50 | 40 | 800000 | 16000 | 0.0 |
| 1024000 | 24000000 (ACLK) | 64 | 23 | 1043478 | 16304 | 1.9 |
| 1280000 | 24000000 (ACLK) | 80 | 19 | 1263157 | 15789 | -1.31 |
| 800000 | 24000000 (ACLK) | 50 | 30 | 800000 | 16000 | 0.0 |